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We present circuits for efficient repeaterless on-chip wires. A transmitter sends RZ pulses to a clockless hysteresis receiver using a 3-tap FIR filter to control ISI. Partly overlapped bits double bandwidth using adaptive pre-emphasis. A 90 nm CMOS testchip shows bandwidth density of 4.4 Gb/s/??m over 5 mm on-chip links with 0.34 pJ/b energy consumption.
This paper compares the energy-delay tradeoff curves of 32-bit static barrel and funnel shifters. The Stanford Circuit Optimization Tool (SCOT) is used to determine best transistor sizes in a 90 nm process. The paper evaluates the effect of multiplexer valency, circuit design, and physical placement. It also quantifies the costs of various shift operations. A funnel shifter using 4- and 8-input static...
Thirty-four undergraduates implemented a MIPS R2000 processor for an introductory CMOS VLSI design course. This included designing a microarchitecture in Verilog, developing custom PLA generation and ad-hoc random testing tools, creating a standard cell library, schematics, layout, and PCB test board. The processor was fabricated by MOSIS on an AMI 0.5-micron process, included 160,000 transistors,...
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