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The main cause of errors in the navigation of the Global Positioning System (GPS) satellite is the ionospheric delay. Therefore, ionospheric delay forecasting studies play an important role in the reduction of the positioning error. This paper focuses on forecasting of ionospheric delay using the statistical Holt-Winter method during the quiet and disturbed days in October 2011, using GPS Ionospheric...
Located in Southeast Asia, Indonesia and the Philippines are characterized by a tropical climate and high amounts of rainfall that render their high potential for hydro-power and wind energy deployment. The volcanic geography of both countries also indicates their high geothermal potential compared with that of other countries, and their high solar radiation level makes them suitable areas to establish...
The objective of this paper is to observe the improvement of engineering graduates by comparing the employers' perception in the past and present, towards attributes owned by engineering graduates in their workplace. The data collected through face-to-face and telephone interviews with employers from Kelang Valley area of Malaysia in 2010 and from employers across sectors in various regions of Malaysia...
In this paper, Taguchi method was used to analyze of input process parameters variations on threshold voltage (VTH) in 45nm n-channel Metal Oxide Semiconductor device. The orthogonal array, the signal-to-noise ratio, and analysis of variance are employed to study the performance characteristics of a device. In this paper, there are eight process parameters (control factors) were varied for 2 and 3...
This paper describes growth process of the two silicide Sub-nanometer devices and the different effects of having cobalt silicide and titanium silicide on a Sub-nanometer CMOS devices. On the top of CMOS device gate, metal silicide is developed on-top of the polysilicon to produce an ohmic contact between the polysilicon and aluminum wire. The ohmic contact should be better compared to metal-polysilicon...
CMOS transistor reaches physical and electrical limitations technology passes through the critical 90 nm gate size. Scaling down linearly to 35nm, the transistor electrical characteristics behave even more unpredictable. This can be seen with leakage current increasing exponentially as the physical size reduced linearly, mainly caused by the short channel effect. As a result, the threshold voltage...
In an earlier publication, the authors have proposed a model on practical framework of engineering employability skills, i.e. the Malaysian Engineering Employability Skills (MEES). The framework discusses on the possible employability skills as required for an entry level engineer in Malaysia based on many other earlier studies. A set of questionnaires was later developed to gauge this model from...
Taguchi method was used to optimize of the effect process parameter variations on threshold voltage in 45nm NMOS device. In this paper, there are four process parameters (factors) were used, which are Halo Implantation, Source/Drain (S/D) Implantation, Oxide Growth Temperature and Silicide Anneal temperature. The virtual fabrication of the devices was performed by using ATHENA module. While the electrical...
In this paper, we investigate the impact of process parameter like halo structure on threshold voltage (VTH) and leakage current (ILeak) in 45nm NMOS device. The settings of process parameters were determined by using Taguchi experimental design method. Besides halo implant, the other process parameters which used were Source/Drain (S/D) implant and oxide growth temperature. This work was done using...
Taguchi method was used to analyze the experimental data in order to get the optimum average of silicide thickness in 45nm devices. The virtually fabrication of the devices was performed by using ATHENA module. While the electrical characterization of the devices was implemented by using ATLAS module. These two modules were used as design tools and helps to reduce design time and cost. In this paper,...
The characteristics of high performance 45 nm pMOS devices based on International Technology Roadmap for Semiconductor (ITRS) have been studied using ATHENA and ATLAS's simulator. There are four factors were varied for 3 levels to perform 9 experiments. The factors are halo implantation, Source/Drain (S/D) implantation, oxide growth temperature and silicide anneal temperature. In this paper, Taguchi...
GPS is of great importance in precise positioning, however, the accuracy is marked by error sources, i.e. ionospheric effects. The signal information is delayed and the carrier phase experiences an advance due to the dispersive character of the ionosphere. The delay can be more than 100 meters in the worst case scenario and tends to increase with increasing solar activity. This error can be corrected...
In this study, effect of various moisture condition on underfill interfacial adhesion loss were examined using C-SAM, 4-point flexural bend test, and cross sectional analysis. In addition, weight gain analysis was used to determine packages moisture absorption at preconditioning level. In order to understand mechanical properties degradation of underfill material, 4-point flexural bending test was...
The purpose of this study is to discuss on the effect of high temperature storage (HTS) on lead free solder joint material for ball grid array application using pull test method. Three samples of different lead free solder joint material were choosed in this experiment that are Sn3.8Ag0.7Cu (SAC387), Sn2.3Ag0.08Ni 0.01Co (SANC), and Sn3.5Ag. Then the lead free solder joint material samples were subjected...
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