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7nm CMOS FinFET technology featuring EUV lithography, 4th gen. dual Fin and 2nd gen. multi-eWF gate stack is presented, providing 20% faster speed or consuming 35% less total power over 10nm technology [1]. EUV lithography, fully applied to MOL contacts and minimum-pitched metal/via interconnects, can reduce >25% mask steps with higher fidelity and smaller CD variation. AVT of 6T HD SRAM cell are...
We discuss the transition to Ti based silicides for source-drain (SD) contacts for 3D FinFET devices starting from the 14nm node & beyond. Reductions in n-FET & p-FET contact resistances are reported with the optimization of metallization process & dopant concentrations. The optimization of SiGe epitaxy and addition of a thin interfacial NiPt(10%) are found to significantly improve p-FET...
A 60 GHz improved IIP3 double-pole double-throw (DPDT) switch using body and gate floated multi-stack resonator implemented in 65 nm CMOS technology is presented. To improve the IIP3, multi-stack and resistive body-floating techniques are used. To decrease the insertion loss, the resistive body-floating, gate-floating and resonant inductor techniques are used. This DPDT switch is designed to have...
Embedded non-volatile memory (NVM) introduces additional thermal processes to a logic process flow and the impact from this extra thermal budget becomes more considerable with continued device scaling. This paper investigates the mechanism of SRAM VMIN degradation in a 40nm embedded NVM process and provides a solution to address the degradation caused. Failure analysis shows enlarged poly grain size...
We evaluate the operating conditions of the cascaded intensity and phase modulators used for the generation of the optical frequency comb lines having the sharpest spectral edges for a given spectral flatness. These operating conditions (to achieve the sharpest spectral edges) are different from those for the best spectral flatness. By operating the cascaded intensity and phase modulators with these...
In this paper, we present a 64nm pitch integration and materials strategy to enable aggressive groundrules and extendibility for multi-node insertions. Exploitation of brightfield entitlements at trench and via lithography enables tight via and bi-directional trench pitch. Setting the same mask metal spacing equal to CPP maximized density scaling and speed of standard cell automation by avoiding cell...
In this paper, we present a high performance planar 20nm CMOS bulk technology for low power mobile (LPM) computing applications featuring an advanced high-k metal gate (HKMG) process, strain engineering, 64nm metal pitch & ULK dielectrics. Compared with 28nm low power technology, it offers 0.55X density scaling and enables significant frequency improvement at lower standby power. Device drive...
Address resolution protocol (ARP) is widely used to maintain mapping between data link (e.g.MAC) and network (e.g. IP) layer addresses. Although most hosts rely on automated and dynamic management of ARP cache entries, current implementation is well-known to be vulnerable to spoofing or denial of service (DoS) attacks. There are many tools that exploit vulnerabilities of ARP protocols, and past proposals...
As the current-carrying capability of a copper line is reduced due to interconnect dimension shrinkage, self-aligned CoWP metal-cap has been reported to be helpful to improve degraded electromigration (EM) reliability. However, adoption of the metal cap in general further exacerbates the already problematic low-k dielectric TDDB reliability at 32nm and beyond. This paper provides a comprehensive study...
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