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State-of-the-art silicon interposer technology of chip-on-wafer-on-substrate (CoWoS®) has been applied for the first time in fabricating high performance wafer level system-in-package (WLSiP) containing the 2nd-generation high bandwidth memory (HBM2). An ultra-large Si interposer up to 1200 mm2 made by a two-mask stitching process is used to form the basis of the 2nd-generation CoWoS® (CoWoS®-2) to...
A novel 3D InFO inductor is developed to integrate with TSMC 16nm FinFET devices for high efficiency integrated voltage regulator (IVR) design. The 3D InFO inductor is designed using thick through-InFO-via (TIV) copper, where the form factor is 1.4 × 2.2 × 0.15 mm3. It performs 2.14 nH inductance at 140 MHz and 3.2 mΩ resistance at DC. The resistance of power delivery network (PDN) between inductor...
This papers reports on the study of two wafer level underfills (WLUF) for 3D stacked IC applications. WLUF either as a liquid (material A) or a dry-film (material B) were applied at wafer level before singulation and stacking in a die to die configuration using a thermo-compression bonding (TCB) process. The materials were applied on the top die on Cu/Sn microbumps 8.5μm thick to reach a film thickness...
In this work the effects of 3D stacking technology on the performance of devices are systematically studied. For this study a special chip consisting of a number of stress sensors and vertical interconnect loops was designed and manufactured in 65nm technology. Local variations of stress with a magnitude of up to 300 MPa are detected at different locations along the chip and are being characterized...
We demonstrate for the first time 3D multi-tier (N=4) 50μm thin die bonding for 3D IC technology using low bonding temperature and pressure for Cu TSVs bonded on Cu bumps with a cost effective structure. Die-to-die (D2D) thermal compression bonding (TCB) process with scrubbing is carefully studied in order to improve the bump height TTV and surface roughness. The bonding temperature and pressure can...
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