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In this paper, the improved field-effect diode (FED) has been characterized and modeled in 45 nm silicon-on-insulator (SOI) technology. It has been experimentally shown to be suitable for pad-based local clamping under normal supply voltage (Vdd) range (below 1 V) in high-speed integrated circuits. ESD protection capabilities are investigated using very fast transmission line pulse (VF-TLP) tests...
In this paper, we present a comparison of the turn-on voltage between SOI-SCR, and the novel DWFED structure. We show that DWFED can achieve faster turn-on, protecting the low voltage devices more effectively. Using the pulse waveforms, we justify the use of a gate trigger circuit for the DWFED to reduce the transient spikes under faster CDM pulses.
This work focuses on characterization, modeling, and design of three different ESD protection devices for high-speed I/O applications in 45 nm silicon on insulator (SOI) technology. In this paper, the gated diode, the bulk substrate diode, and a double-well field-effect diode are evaluated using very fast transmission line pulse (VF-TLP) test method.
This article deals with the importance of the structure of FED, that lies in the fact that by appropriately biasing it, its operation can be switched between SCR-like and diode-like. For devices with p-type body doping the depletion of electrons beneath G1 imposes an upper limit to the breakdown voltage. This paper proposes to use n-type body doping instead to achieve high breakdown voltage and reduce...
The double well field effect diode (DWFED), an SOI SCR-like device for ESD protection of I/O circuits, is presented. The effect of device and process parameters on the diode on-voltage is examined, and the TLP and VFTLP characteristics of the DWFED are compared with those of the SOI lateral diode. It is shown how to use the DWFED for local clamping ESD protection, with a diode-like It2 level.
In this paper the authors present the field effect diode (FED) as a novel device with a new approach for ESD protection in SOI. Device parameters are identified and optimized to achieve optimum ON and OFF behavior. Furthermore, the authors present two ways the FED can be used in an ESD protection scheme: in I/O clamping and in a high-voltage supply clamp
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