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Advanced NAND flash memory requires higher cell density [1–2]. With the gate pitch critical dimension (CD) of NAND flash memory drops to sub-50nm or even lower, numerous process problems occur [3]. Poly gate etching, evolving CG and FG formation, as the dominator for the poly gate profile, confronts critical challenges as the line fluctuation known as wiggling, side wall bowing, depth micro-loading...
With the shrinkage of pattern CD (Critical Dimension), pattern collapse, micro-loading effect and silicon to silicon dioxide selectivity become more challenging in STI (Shallow Trench Isolation) patterning. Pattern collapse is closely related to micro-loading effect. To enhance Si to SiO2 selectivity and suppress micro-loading effect, bias RF pulsing and cycle etch are used [1]. In this paper, the...
Single PR (photoresist) photo works well in implantation process for planar transistors, however, it suffers severe PR residue issue in FinFET technology node due to the three dimensional fin/gate structure and large wafer surface topography. New integration scheme with BARC (Bottom Anti-Reflective Coating) coating/etching was developed to solve this problem. In this work, BARC etching process was...
For advanced node such as 14nm technology and beyond, tradition immersion photolithography transforms to double patterning, EUV or negative tone development (NTD) technology to improve pattern transfer techniques. Even through, a pattern wiggling issue has arisen with the reduction of pattern dimension during substrate dry etch, which prevents the successful pattern transfer. In this paper, two kinds...
FinFET technology has been chosen for extending CMOS scaling beyond 28nm node. It can improve short channel control through a fully depleted fin, reduce random dopant fluctuation, improve mobility, lower parasitic junction capacitance and improve area efficiency. The non-SAC (self-aligned contact) local interconnection is introduced for the device connection. As the pitch shrinkage beyond immersion...
In this paper, we present a 1T1R (one-transistor-one-resistor) structure RRAM (resistive switching random access memory) fully integrated with existing CMOS process. The RRAM cell is fabricated between two metal layers (metal A and metal B), and consists of plug contact type bottom electrode (plug-BE), resistive layer and top electrode (TE). As the RRAM cell is an island pattern, there are some issues...
In the past several decades, the NAND flash memory encounters a great scaling of floating gate cell [1]. With the scaling of floating gate cell below 2X node, challenges related to the physical and electrical issues emerge. In the cell contact formation, dimension shrink and bowing profile related to the high aspect ratio seems to be difficult to overcome. The gap between lithography tools and cell...
Pulsed capacitively coupled plasmas (CCP) was applied to self-aligned-via (SAV) based all-in-one (AIO) etching process. Effects of bias and synchronous pulsed plasmas on the AIO etching process were analyzed to improve the reliability and reduce the RC delay in back-end-of-line (BEOL) copper interconnect system. For steps of hard-mask open and partial via etch, synchronous pulsed plasmas were applied...
As logic technology keeps shrinking to 28nm and below, Ultra Low-£ (ULK) dielectric film is widely used in BEoL (Back End of Line) to improve RC performance. To reduce k value damage, weaker post dry-etch cleaning is used to avoid methyl group loss, but the etch by-product removal capability is reduced also. Even with softer cleaning, the trench and via profile still will be affected due to ULK film...
Gate last approach has started to appear in the high performance applications since 45nm technology node. Such approach has to leverage soft wet and asher process for the polymer and byproduct removal after the 2nd DPGR for the 1st DPGR metal damage concern. However, it's well known that it's hard for soft wet process to remove all byproduct. Even worse, the rich polymer inside trench could result...
As CMOS process is advancing towards the high-k/metal gate (HK/MG) technology, dummy poly gate removal (DPGR) process, one of key steps in gate-last technology, poses the challenge for its multiple-film related etching process. Its subsequent photo-resist (PR) strip process is also very difficult due to rigorous process requirements and rather limited wet clean resource. The DPGR process in this work...
With the number of telecom users and business volume increasing year by year, the traditional paper-made work orders has been unable to meet the needs of telecom companies and users because of low circulation efficiency, high cost, high failure rate and other drawbacks, the rapid development of computer technology makes office automation become the trend of future business development. Aiming at this...
When CMOS technologies entered nanometer scales, FinFET has become one of the most promising devices because of its superior electrical characteristics. To accommodate the 3D topography, gate etch needs soft landing on the top of Fin while removing the extra poly-si around Fin. Its over etch is more aggressive than conventional planar gate to avoid poly-si residue. Fin loss should be well controlled...
Both shallow junction and HKMG have been integrated into the advanced logic process. This leads to the introduction of forming gas (4% H2 in N2/H2 mixture) to replace the traditional O2-based ashing process for the sake of material loss and metal oxidization in Lightly Doped Drain ash. In this work, we focused on the high volume H2 ashing not only from the point of view of physical performance but...
Since CMOS technology moved to sub-40nm node and beyond, the remarkable challenges have been noticed in dry etch, wet clean and the subsequent metal deposition process of contact loop. Contact etch has been proven as one of the most critical roles for yield enhancement. It not only needs to overcome the incoming challenges such as poor PR profile/CDU and CESL (Contact Etch Stop Layer) nitride pinch-off,...
Be directed against the situation where grain's hot and mildew cannot be solved in time in the granary, which leads to loss, this thesis designs a kind of intelligent granary monitoring system which can realize real-time and remote monitoring in the process of grain storage. The system can be used to measure, display each point's temperature and humidity in the granary, control windows, high-power...
This paper presents an overview of 65 nm poly gate fabrication challenges emerged during the device performance & yield enhancement on 300 mm wafer. The proposed solutions hinge on the improvement of some critical process parameters in 65 nm gate etch such as, critical dimension uniformity (CDU), through-pitch etch bias (TPEB), line width roughness (LWR) and poly gate profile. More than 7% yield...
65 nm BEOL trench etch is apt to suffer the marginal PR issue. It is a big challenge for trench etch process to simultaneously satisfy the requirements for both metal resistance (Rs) and breakdown Voltage (VBD). The copper surface condition of via bottom is a big concern of trench etch process as well. In this paper, we present several electrical parameter issues that occurred at 65 nm trench etch...
The mechanism of two kinds of via etch striation (type I and type II) has been investigated to improve contact resistance (Rc) uniformity and solve breakdown voltage (VBD) issue in 65 nm Cu low-k interconnects. Heavy etching polymer deposition on the sidewall of capping layer and rapid photo-resist (PR) consumption on PR shoulder are two main resources to result in via etch striation. The effects...
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