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This paper discussed the applications of electron energy loss spectroscopy (EELS) for element characterization in semiconductor manufacturing. The first experiment compared the ability of element chemical states analysis between EELS and X-ray photoelectron spectroscopy (XPS). Some phase change random access memory (PcRAM) product suffered TiN connection electrode failure. EELS and XPS were used separately...
In this paper, we reported a EVB Burn In (B/I) failed case of our ABCD part and led to the finding of VIA process fabrication issue with TiN film process marginal issue. This EVB B/I failed case was carried out by electrical failure analysis (EFA) and physical failure analysis (PFA) using FIB X-section and TEM. This paper also demonstrated different EFA technology, which included curve tracer analysis,...
Package Level Threshold Voltage Stability (VTS) evaluation on PMOS has emerged as one of the critical reliability concerns in deep sub-micron devices. In this paper, we present a novel method to fast measure VTS at wafer level. Our result shows that changing the Source/Drain IMP species can improve the VTS of a 0.13um Flash.
In this paper, a source/drain design for vertical channel nanowire FETs involving extension doping profile, spacer dielectric constant and spacer width is proposed and demonstrated by TCAD simulation. The results show that asymmetric graded lightly doped drain (AGLDD) exhibits excellent SCE controllability and driving capability even with relatively large nanowire diameter. By adopting high-k spacer...
In this work, we investigated the influence of retrograde-well implantation on hetero-structure body-tied germanium (Ge) FinFET [1]. Using structural engineering, the retrograde well was fabricated prior to Ge epitaxy, which could avoid the activated temperature of dopant in Si substrate. With optimizing the implant condition, the p-Ge/n-Si hetero-structure junction exhibited high ION/IOFF ratio and...
Static Random Access Memory (SRAM) is a preferable test vehicle even when semiconductor technology scales down to 28nm node. To tolerate aging induced SRAM device degradation, a higher Vccmin window at Time Zero (T0) is needed to ensure SRAM HTOL (High Temperature of Lift Time) reliability performance. However, Vccmin shift outlier is often observed post HTOL stress, which cannot be explained as device...
In this paper, a new class of layout dependent effects (LDE)—the time-dependent layout dependency due to device aging, is reported for the first time. The BTI and HCI degradation in nanoscale HKMG devices are experimentally found to be sensitive to layout configurations, even biased at the same stress condition. This new effect of layout dependent aging (LDA) can significantly mess the circuit design,...
This article describes a time-domain near-field planar measurement system constructed in an anechoic chamber. Distinct from conventional radar cross section (RCS) frequency domain system, the time domain measurement system consists of time domain facilities can obtain RCS results in a wideband by a measurement. Meanwhile, a weighted window function method brought in the process of near-field to far-field...
The path planning problem is of essential significance for the theoretical research and practical applications of mobile robot navigation. However, it is found to be non-deterministic polynomial time hard (NP-hard) problem. Aiming at solving the problem of the large computational complexity, an adaptive quantum evolutionary algorithm with improved population initialization, adaptive quantum gate operation,...
The electrical and physical properties of PrxAl2−xO3 on metal-oxide-semiconductor gate dielectric were investigated. Amorphous PrxAl2−xO3 films with the thickness of 15 nm were deposited by electron-beam evaporation under a typical dielectric constant and equivalent oxide thickness of 18 and 3.3 nm, respectively. Leakage current decreased from 48mA/cm2 to 3.4mA/cm2 at a gate voltage of 1V after 500...
The electrical and physical properties of PrxAl2−xO3 on metal-oxide-semiconductor gate dielectric were investigated. Amorphous PrxAl2−xO3 films with the thickness of 15 nm were deposited by electron-beam evaporation under a typical dielectric constant and equivalent oxide thickness of 18 and 3.3 nm, respectively. Leakage current decreased from 48mA/cm2 to 3.4mA/cm2 at a gate voltage of 1V after 500...
As a promising transistors beyond 22nm technology node, Silicon nanowire (Si NW) transistor has attracted a lot of attentions recently [1]-[4]. Due to its unique gate-all-around (GAA) structure, Si NW transistor provides enhanced gate controllability and reduced sub-threshold leakage. However, gate-induced drain leakage (GIDL) as another primary leakage mechanism is still challenging [5][6]. In addition,...
We propose and analyze a novel concept for all-optical NOT gate (AONG) for high-speed telecommunication on-off-keying data signals based on spectral phase-only linear optical filtering, with applicability for speeds above 160Gb/s. Proof-of-concept experiments are reported to validate the proposed AONG working principle.
Novel designs for high-efficiency millimeter wave zero-bias detectors are presented. As the renowned backward diodes are extensively exploited in the utilization of zero bias detectors due to its preferable conduction for small reverse biases, the single-handed diode detectors reveal its inherent capabilities by the semiconductor processes which the detectors are made from. The selected process chiefly...
Sub systems of complex system or platforms under network centric warfare (NCW) condition are required to work collaboratively in order to achieve an overall mission objective. It is very difficult to model and analyze the reliability of this kind of multiplatform phased mission system (PMS). At first, this paper sums up the characters of multiplatform PMS, and then put forward the method of mission...
A driver for high-voltage (HV) single chip synchronous buck converters with a n-channel lateral double diffused MOS (nLDMOS) as power switches and a high speed low power level shifter is presented. Using a short time fast speed pull-down circuit, the level shifter realized high speed with a limited bias current. The circuit is implemented using UMC 0.5-μm 30V LDMOS process, and has been integrated...
Fabrication and performance of high-frequency 0.3-μm gate-length depletion-mode metamorphic Al0.50In0.50As/Ga0.47In0.53As high electron mobility transistors (mHEMT) grown by Metalorganic Chemical Vapor Deposition (MOCVD) on n-type silicon substrates is reported. Using a combined optical and e-beam photolithography technology, submicron mHEMT devices on Si have been achieved. A maximum trans-conductance...
FLUTE is a file delivery protocol whose operation can only require a unidirectional communication channel from a sender to a receiver. Due to the nature of unidirectional delivery, FLUTE is designed in a flexible way so that it can cooperate with different kinds of forward error correction codes in application layer, such as systematic Raptor codes or other FEC codes defined in IETF. Besides, since...
We have proposed gate-all-around Silicon nanowire MOSFET (SNWFET) on bulk Si as an ultimate transistor. Well controlled processes are used to achieve gate length (LG) of sub-10nm and narrow nanowire widths. Excellent performance with reasonable VTH and short channel immunity are achieved owing to thin nanowire channel, self-aligned gate, and GAA structure. Transistor performance with gate length of...
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