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In this paper, we investigated the reliability test for Glass interposer. The test vehicle is assembled glass interposer with chip, BT substrate, and PCB. The structure of a glass interposer with two RDL on the front-side and one RDL on the backside had been evaluated and developed. Key technologies, including via fabrication, topside RDL formation, micro-bumping, temporary bonding, silicon and glass...
In this paper, we investigated the assembly characterization for reliability test. The structure of a glass interposer with two RDL on the front-side and one RDL on the backside had been evaluated and developed. Key technologies, including via fabrication, topside RDL formation, micro-bumping, temporary bonding, glass thinning and backside RDL formation, were developed and integrated to perform well...
Three dimensional integration circuits technology has received much attention recently since the demands of functionality and performance in microelectronic packaging for electronic products are rapidly increasing. For high-performance 3D chip stacking, high density interconnections are essential. In the current types of interconnects, solder micro bumps have been widely used and thermocompression...
Recently, three dimensional integration circuits technology has received much attention since the demands of functionality and performance in microelectronic packaging for electronic products are rapidly increasing. For high-performance 3D chip stacking, high density interconnections are required. In the current types of interconnects, solder micro bumps have been widely adopted. For fine pitch solder...
A novel assembly process was developed for ultra-thin chip stacking technology where wafer-level-packaging (WLP) was adopted and combined with chip-on-wafer (CoW) technology. By such assembly process, thin chip handling would be unnecessary in this process. After assembly process, chip thickness within the chip stack could be thinned down to a thickness of 30µm or less than 30µm. Sheet-type molding...
Recently, three dimensional integration circuits technology has received much attention because of the demands of gradually increasing functionality and performance in microelectronic packaging for different types of electronic devices. For 3D chip stacking, high density interconnections are required in high-performance electronic products. Though the bumping process used could be either electroplating...
As the demands of functionality and performance for electronic products increase, three-dimensional chip stacking with high-density I/O has received much attention. For high density interconnections packaging, solder micro bumps are adopted extensively. However, its process temperature is high during chip stacking process. High bonding temperature would be easy to lead chip damage and chip warpage...
As the demands for high density 3DIC stacking increase, a fine-pitch chip-to-chip interconnects is becoming imperative. In conventional flip-chip technology, anisotropic conductive film (ACF) has been used in place of solder and underfill for chip attachment to substrates in some applications, because it provides many advantages. Generally speaking, ACF consists of an adhesive polymer matrix with...
In order to meet the demands of high-performance, high-speed, small form factor and multi-function integration in portable electronic products, the development of packaging technology now trends toward system-in-package (SiP) technology. Three-dimension (3D) integrated circuit technology provides a way to integrate complex micro systems through vertical interconnections among individual devices/chips...
For evaluating the feasibility of adhesive bonding by NCF (non-conductive film) in micro bump joints, three types of micro joints were adopted in this study. The structure of the type I micro joints was Cu/Ni/Au while that of the type II micro joints was Cu/Ni/Au micro bump joined with Cu/Sn solder micro bump. Both the type I and type II micro joint were bonded by using NCF. The structure of the type...
With the increased demand of multifunction in electronic device, downscaling of interconnection pitch presents an important role for the next generation electronics with high performance, small form factor, low cost and heterogeneous integration. In the current types of interconnects, solder micro bumps have received much attention due to its low cost of material and process. For fine pitch solder...
This paper will highlight recent developments of an efficient assembly technology for chip stacking which utilizes a novel wafer applied underfill (WAUF). The a-stage WAUF was spin coated on an 8” wafer with a bump structure of 5 um Cu / 3 um Ni / 5 um Sn2.5Ag Pb-free solder, and then baked at 125°C for 40 minutes to form a 30 um thick b-stage film. After wafer dicing, four chips with WAUF were assembled...
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