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Fine-grained power management of largely-integrated manycore systems is becoming mainstream in order to deal with tight power budgets. As a result, some level of asynchrony is becoming inevitable for efficient system-level operation. Asynchronous interconnection networks naturally provide such asynchrony, however their wide industrial uptake depends on the capability to overcome two fundamental barriers:...
Asynchronous interconnect technology leveraging transition signaling bundled-data is gaining momentum as a promising solution for the chip-level connectivity of GALS (Globally Asynchronous Locally Synchronous) integrated systems. However, the scope of most previous bundled-data network-on-chip (NoC) validations is limited to NoC switches in isolation. Studies with a broader scope admittedly end up...
An asynchronous high-performance low-power 5-port network-on-chip (NoC) router is introduced. The proposed router integrates low-latency input buffers using a circular FIFO design, and a novel end-to-end credit-based virtual channel (VC) flow control for a replicated switch architecture. This asynchronous router is then compared to an AMD synchronous router, in a realistic advanced 14nm FinFET library...
Most multi- and many-core integrated systems are currently designed by following a globally asynchronous locally synchronous paradigm. Asynchronous interconnection networks are promising candidates to interconnect IP cores operating at potentially different frequencies. Nevertheless, post-fabrication testing is a big challenge to bring asynchronous NoCs to the market due to a lack of testing methodologies...
Arbiters are the most critical element to manage a shared resource. Many arbiters in the literature are asynchronous, in order to improve concurrency and make the performance independent from the working frequency of the requesting clients. However, in asynchronous designs, architectural imbalances or variability can affect impartiality, such as latency equalization and arbitration fairness. Such...
NoC-Based Dynamic Reconfigurable Systems (DRSs) implemented over FPGA devices change their configuration at the run time by re-positioning or replacing the existing processing modules into the network. Several Dynamically Reconfigurable NoCs (DRNoCs) in the literature, propose adaptive routing algorithms in order to handle the network structure alteration. Nevertheless, their implementation cost is...
In on-chip interconnection networks, performance optimization techniques can be often achieved in two opposite ways: by making control logic more complex inside switches, or by pushing design complexity to the switch boundaries. The implementation of virtual channel (VC) flow control is an important application domain of this design trade-off. The data path of VC switches typically exhibits replicated...
Several simulations have been performed in order to verify the system architecture behavior, showing that the dynamic reconfiguration time overhead is mainly due to the packet draining time. The synthesis results obtained a maximum frequency of 182.02MHz (Virtex 4) and 162.86MHz (Virtex 6) for both 5×5 and 8×8 meshes respectively. Table I shows the synthesis results for a 5-port 16-bit router and...
MMU-less embedded systems are the state of the art solution for deeply embedded computing environments. Thanks to the rapid evolution of such devices, nowadays applications that run on top of them are evolving from simple control tasks to more complex applications that involve an Operating System (OS). At the same time, cost budget remains unchanged in spite of the growing performance requirements...
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