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Printed electronics (PE) on flexible substrates is a promising technology for wearables and internet of things (IoT). To implement an integrated system on flexible substrates for applications ranging from medical imaging to disposable thermometers, robust design methodology based on unreliable printed components plays a critical role. This paper reviews robust design of printed circuits based on thin-film...
The susceptibility of on-chip communication links and on-chip routers to faults has guided the research towards focusing on fault-tolerance aspects of 2D and 3D Network-on- Chips (NoCs). In this paper, we propose Logic-Based Distributed Routing for 3D NoCs (LBDR3D), a scalable, re-configurable and fault-tolerant mechanism, which utilizes only two virtual channels for implementing any deadlock-free...
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Nowadays chip multiprocessors tend to have an increasing number of cores, usually implementing a distributed shared last level cache. The network on chip (NoC) is in charge of interconnecting the cores, memory controller(s) and cache banks, largely impacting memory access latency. Packet switching in usually used in NoCs, but circuit switching may achieve better performance if the setup time of the...
The Network-on-Chip (NoC) is the preferred interconnection medium for massively parallel platforms. Targeting real-time applications, fixed-priority based NoCs with virtualchannels have been proposed as a promising solution. In order to verify if specific time requirements can be satisfied, schedulability tests are typically used. Several analysis approaches have been proposed targeting priority-based...
All the cores of a many-core chip cannot be active at the same time, due to reasons like low CPU utilization in server systems and limited power budget in dark silicon era. These free cores (referred to as bubbles) can be placed near active cores for heat dissipation so that the active cores can run at a higher frequency level, boosting the performance of active cores and applications. Budgeting inactive...
Fault tolerance and energy consumption are two key aspects of future Network-on-Chips (NoCs). The utilization of deflection routing and Banyan networks for fault-tolerant and energy efficient router architectures was proposed recently. Compared to traditionally deployed crossbars, Banyan networks can reduce hardware costs and improve the energy efficiency of router architectures. However, they also...
Real-world applications exhibit time varying traffic volumes and patterns (structures). However, regular or application specific networks-on-chip (NoC) optimized at designtime are predominantly developed either under the assumption of time independent application structures and dynamics, or without considering them at all. The limited adaptability of the monolithic NoCs to spatio-temporal application...
Most multi- and many-core integrated systems are currently designed by following a globally asynchronous locally synchronous paradigm. Asynchronous interconnection networks are promising candidates to interconnect IP cores operating at potentially different frequencies. Nevertheless, post-fabrication testing is a big challenge to bring asynchronous NoCs to the market due to a lack of testing methodologies...
Several studies have been made on comparison between synchronous and asynchronous NoCs (Network-on- Chips). However, very few attempts have been made at fair comparison between synchronous NoCs designed by synchronous researchers and asynchronous ones designed by asynchronous researchers under the same functional specification using the same fabrication technology. In this paper, representative routers...
A network topology with low average shortest path length (ASPL) provides efficient data transmission while the number of nodes and the number of links incident to each node are often limited due to physical constraints. In this paper, we consider the construction of low ASPL graphs under these constraints by using stochastic local search (SLS) algorithms. Since the ASPL cannot be calculated efficiently,...
We consider the design of a shared global on-chip communication medium using repeated equalized transmission lines (RETLs). Our design overcomes a number of limitations with previously proposed shared global mediums based on transmission lines. Prior solutions require wide-pitch transmission lines that occupy considerable area, do not support multicast or broadcast operations, and employ centralized...
This paper reviews various optical switch technologies, then discusses how to realize an optical circuit switching interconnect capable of more than 10 Tbps link bandwidth and more than 100,000 end points scalability for datacenters or high performance computers. Introducing the wavelength division multiplexing transmission technology and a simple distributed-like control scheme of optical switches...
Hybrid systems combine Large-Area Electronics (LAE) with high-performance technologies (e.g., silicon CMOS) [1]. With architectural concepts for hybrid systems broadening to match the range of emerging applications, this paper examines modular approaches for multi-sheet, multi-technology integration. It identifies the interfaces required as a critical backbone. For interfaces associated with various...
Recent advances in photonics technologies have made optical interconnection network an attractive option for computing systems from high-performance computers and data centers to automobiles and cellphones. Optical interconnection network promises ultra-high bandwidth, low latency, and great energy efficiency to alleviate the inter-rack, intra-rack, intraboard, and intra-chip communication bottlenecks...
Artificial Intelligence (AI)-based big data analysis is emerging for broad application fields, including manufacturing, autonomous car, health care, agriculture, and so on. Data centers are under severe pressure to meet ever-increasing demands on clouds. On the other hand, the amount of data processing is bounded by the total power budget, where the reasonable number is up to 20 MW. Therefore, the...
Emerging flexible hybrid electronics paradigm integrates traditional rigid integrated circuits and printed electronics on a flexible substrate. This hybrid approach aims to combine the physical benefits of flexible electronics with the computational advantages of the silicon technology. In this paper, we discuss the possibility to implement a physically flexible system capable of sensing, computation...
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