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This work describes an innovative low-loss transmission line routing configuration, which enables improved channel margin in next-generation high-speed serial buses beyond 10Gbps applications. One such example is SuperSpeed Plus USB a.k.a. USB 3.1 Gen2. Ultimately, this novel routing when implemented in either substrate or printed circuit board (PCB) will extend platform length within the interconnect...
The rising demands of miniaturize and high performance electronic gadgets necessitates higher density with higher bandwidth interconnect which is being limited by prevailing microwave effects as signaling data-rate surges and routing pitch shrinks. This paper presents a transmission line design with three-dimentional (3D) reference plane to alleviate the signaling crosstalk impacts that limit the...
This paper investigates and discusses the impact of surface roughness on package insertion loss performance for high-speed applications up-to 50GHz. 3D electrical package with Hurray surface roughness modeling was established and simulated. The insertion loss performance of package interconnects are discussed and compared against laboratory measurement results. The magnitude of electrical insertion...
Maximum current (Imax) distribution across substrate has been one of the major design factors that govern the electronic package form factor. Particularly on ball grid array (BGA) package design, often times Imax distribution determines the number of solder balls required for each interface to sustain respective workloads hence defines the total ball count and the x-y dimension of the electronic package...
This paper evaluates the impact of dielectric loss tangent property on electrical insertion loss performance for both conventional and coreless packaging designs up-to 100Gbps datarate. Coreless package with metal grid array (MGA) second level interconnect (SLI) that yields minimal impedance discontinuities was observed gaining more than 50% insertion loss improvements i.e. ∼20% higher compared to...
This paper describes a novel segmented plated-thra-hole (PTH) structure in flip-chip packaging design to address the current and future high-speed signaling and power integrity problems. The design is capable to resolve the high-frequency coupling from signal integrity perspective, as well as power integrity's loop inductance and resistance issues, which are commonly associated with today's ultra-small...
This paper explores the effectiveness of under-bump comb (UBC) structure to address the capacitive crosstalk couplings in high-speed on-package interconnects applications. Three-dimensional (3D) passive electrical models were established and simulated in this assessment. Transient analyses were conducted to compare the far-end crosstalk (FEXT) profiles and eye diagrams of the UBC and conventional...
This paper analyzes the electrical performance of standard and coreless packages up-to 100Gbps data rate. The impact of package design attributes e.g. substrate core thickness, plated through hole (PTH) pad dimension and geometry of second level interconnect (SLI) on insertion loss performance are explored in this study. This study also evaluates the electrical performance of an alternative coreless...
This paper presents the crosstalk analysis study for high-speed on-package interconnects in multi-chip package (MCP). The crosstalk coupling effects from adjacent aggressors on signaling performance e.g. eye opening and signal overshoot were investigated in this study. Simulations were performed on both microstrip and stripline structures from 2Gbps up-to 6Gbps. Several key design parameters e.g....
This paper explores the electrical performance of several multi-channel TSV designs i.e. cross-etched full-plated TSV and cross-etched partial-plated TSV to further improve data transmission bandwidth among the vertically stacked silicon devices. The electrical characteristics of the multi-channel TSV designs were investigated and compared against the conventional TSV design in terms of return loss,...
Multi-chip package (MCP) technology has recently advanced as an alternative packaging solution to enable high performance and power-efficient mobile electronic devices. The wide adoptions of MCP technology are mainly driven by reduced circuit complexity, heterogeneous integration across different silicon process technology and shorter product cycle time. However, the high density on-package die-to-die...
The conventional power delivery analysis applying Icc(t) approach has the propensity to yield pessimistic outcome that leads to power delivery network (PDN) over-design. In addition, the noise profile captured using Icc(t) approach has high prospect of miscorrelation with the lab measurement data. Recent works adopting the signal integrity and power delivery (SIPD) co-simulation approach was found...
This paper investigates the sensitivity of channel termination on vertical side-chip interconnection (VSCI), an alternative high density and low z-height enabler for 3D packaging technology. In this study, the trends of eye height opening, one of the critical signaling parameters, were analyzed based on transmission channel length, input rise time, receiver device capacitance and termination resistance...
Multi-Chip Package (MCP) is becoming a customary form of integration in many high performance and advanced electronic devices. The vast adoptions of this technology are mainly contributed by advantages for instance lower power consumption, heterogeneous integration of multiple silicon process technologies and manufacturers, shorter time-to-market and lower costs [1]. However, the high density interchip...
A novel enabling technique exploiting interposer approach such as silicon and package interposer [1] in the area of package-on-package (PoP) technology to achieve ultra small form factor packaging solution is presented in this paper. Electrical performance of such interconnect innovation is discussed and pitted against the conventional PoP methods using solder ball connection, as well as the recent...
This paper presents a novel enabling technique exploiting interposer approach such as silicon and package interposer in the area of package-on-package (PoP) technology to achieve ultra small form factor packaging solution. The electrical performance of such interconnect innovation is discussed in this paper, and pitted against the conventional PoP methods using solder ball connection, as well as the...
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