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A random access analog memory is designed without static power in this work. The analog memory appears the benefit on the great reduction of interconnections but suffers from the static power consumption and inaccuracy. As a hybrid, the hexadecimal signal processing is targeted in this paper. For storing hexadecimal values even implementing hexadecimal sequential logic, a master-slave structure is...
Post-Silicon clock-Skew Tuning (PSST) is a promising technology for improving performance-yield of LSI circuits under process variations. On the other hand, the resultant circuit after clock-skew tuning should be robust also against run-time variations induced by temperature variation, power supply noise, etc. In this paper, the timing margin in the context of PSST is introduced in terms of control...
This paper discusses Dynamically Voltage-Frequency Scaling (DVFS) with a limited number of voltage levels (Multi-Level DVFS (ML-DVFS)), and concurrent optimization of voltage levels and voltage assignment is investigated. Based on Karush-Kuhn-Tucker (KKT) conditions for the optimum solution of our ML-DVFS optimization problem, several properties of the optimum solution of ML-DVFS problem are revealed...
The feasibility of flipflop designs for storing hexadecimal datum is studied in this work. Hexadecimal signal processing appears the benefit on the great reduction of interconnections, which leads to the potential of improving various performances. However, the storage of hexadecimal datum is very challenging for the conventional binary implementations. In this paper, a prototype of hexadecimal flipflop...
Due to the downsizing of VLSI, reliability issues caused by soft-errors have become more explicit. Several studies in system level approach to date have proposed transient fault-tolerant datapaths with comparison-retry based or majority-voting based error correction schemes. In this paper, considering both efficient use of resources and latency reduction, we introduce a combination of the two error...
Power consumption is one of the major concerns for high performance VLSI design. Under the well-known trade-off between power and speed performance driven by the selection supply voltage level, Voltage-Frequency Scaling (VFS) is one of the promising techniques for saving energy while keeping performance requirement. In this paper, we consider multiple tasks to be processed on a single processor with...
As the device size decreases, the reliability degradation caused by soft-errors and multiple component error due to a single soft-error are becoming serious problems in VLSIs. In this study, we propose a method to synthesize single soft-error tolerant datapaths based on soft-error detection by duplication and comparison and correction by retry. Under the assumption that a single soft-error does not...
A field programmable gate array (FPGA) architecture is developed in this work for implementing multi-valued logics (MVL). The arbitrary function of sixteen-valued logic, which is four-bit equivalent to conventional binary circuitry, can be carried out for approximate computations. The number of devices and interconnections in the proposed FPGA processor are both compacted in contrast to those of the...
With the growing scale of integration, it is demand for next-generation VLSI design to consider not only the number of resources, but also the bitwidths of them. Removing wasted bits of resources, the area and power costs are optimized rather than conventional design. This paper shows that intentional clock skew (useful clock skew) is effective to improve the performance of bitwidth-aware circuits,...
As the size of semiconductor devices has decreased, reliability degradation caused by soft-errors has become one of the greatest issues in VLSI circuit design. In this paper, we propose a method to synthesize soft-error tolerant application-specific datapaths via high-level synthesis. Our method is based on a concurrent error detection and a retry mechanism for error detection and error correction...
The feasibility of quaternary field programmable gate array (FPGA) is investigated in this work by using standard CMOS technology and ordinary dual-rail of power supply lines. For quaternary signal processing, the basic functional circuits, quaternary memory unit, look-up table (LUT), and framework of FPGA addressing are proposed. Employing the Neuron-MOS mechanism, multi-threshold voltage inverters...
The combination of triple algorithm redundancy and vote-writeback (TAR/VW) is a promising approach for designing an application specific fault-tolerant datapath circuit. The cone partitioning of an input application algorithm in TAR/VW framework increases the opportunity of resource sharing while keeping the fault tolerance ability. However TAR/VW combined with cone partitioning requires a specialized...
In this paper, we discuss an ILP-based method for simultaneous optimal technology mapping, placement and routing for programmable logic devices, such as FPGAs, as a fundamental research for architecture and algorithm evaluation. In general, heuristic methods are used for technology mapping, placement and routing, and many such methods have been developed. Although they are used to obtain high quality...
Due to an increase in home appliances (HAs) the overall power consumption in home tends to grow and leads an increasing risk of losing stability. In this paper, we propose a system model for smart homes to control maximum power consumption by HAs based on HA priority. The proposed system consists of smart electric sensors (SESs), power provisioning controller (PPC) and HAs. The role of PPC is to gather...
Post-Silicon Tuning is an emerging technology for improving performance-yield of VLSIs under process variations. This paper focuses especially on the post-silicon timing-skew tuning (PSST) via programmable delay elements (PDEs), and proposes a novel tuning algorithm which utilizes only the result of setup and hold timing tests, not the result of costly delay-time measurements. The basic framework...
In the presence of process variation, conventional worst-case timing analysis is no longer able to fully realize the benefit of scaling and integrating. As a result, statistical static timing analysis (SSTA) is essentially needed in high-level synthesis (HLS) stage. This paper presents the first work to develop a design framework of SSTA for HLS based on transparent latches. An integer linear programming-based...
Moving into the era of nanoscale devices, reliable clock distribution becomes a challenging problem due to the growing impact of process variations. This paper deals with this difficulty, especially on implementing useful clock skew. One possible robust way is by using programmable delay elements (PDEs) since PDEs can be adjusted after fabrication. However, with this benefit, using PDEs takes large...
This paper treats post-silicon skew tuning for improving performance yield under various delay variations, and proposes a novel PDE tuning algorithm which utilizes only the result of setup and hold timing tests, not the result of delay measurements. Our algorithm is based on “trial-and-error” approach, and it has a proper level of robustness against the variation of each PDE characteristics. As far...
Nowadays, clock skew becomes a manageable resource to improve circuits by assigning a certain clock delay to each register. However, it has been reported that implementing a large spectrum of dedicated clock delays becomes challenging in a reliable manner under several uncertainties. To overcome this limitation, multi-domain clock skew scheduling (MDCSS) has been proposed, and studied in logic- and...
Clock skew scheduling is a process of assigning intentional clock skews to registers for improving circuit performance and reliability. Due to the recent large effect of process variations, it becomes more and more difficult to reliably implement a large set of arbitrary clock latencies. Consequently, the optimization potential of clock skew scheduling should be highly limited. This paper points out...
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