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This paper describes an application of a physical-design-friendly hierarchical logic built-in self-test (BIST) architecture and validation methodology on a networking system-on-chip (SOC) design. The design consists of two embedded cores, each containing approximately 45 million primitives and 2.5 million flip-flops. The implemented architecture supports an at-speed staggered launch-on-capture clocking...
In this paper, a self-testable SiGe low noise amplifier (LNA) is designed and a Built-in-Self-Test (BIST) methodology is proposed for amplifiers embedded in RF systems. In this BIST methodology, the RF amplifier has the capability to simultaneously test multiple performance specifications on-chip, including Gain and PldB. The self-testable LNA can be placed in a testing mode, in which it self generates...
Adaptive path-delay testing is a testing methodology that reduces redundant test patterns based on the measured process condition of a die under test (DUT). To improve testing efficiency, process conditions are clustered into a limited number of clusters, each of which has a corresponding set of test patterns. The test pattern set of a cluster must include all potential timing-critical paths of all...
3D-SOC technology has significant performance and power gains over 2D as interconnects can be shortened significantly. To accrue full benefits of reduced interconnect lengths large designs need to be partitioned into several dies. In this work we propose a hypergraph based multi-objective circuit partitioning scheme for 3D-SOCs that simultaneously reduces the number of inter die connections, which...
We present a design-for-test apparatus for measuring real-time, on-chip heat map images with high granularity. Our test chip implemented an 8 × 8 matrix of temperature sensors on-chip in a 0.18µm process with minimal area and power consumption overhead. We then implemented a test interface for measuring individual temperatures with an off-chip ADC and a custom FPGA-based microcontroller with serial...
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