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As the pitch of TSVs shrinks down, electrical characteristics of TSV become more complicated and mechanical stress becomes a critical issue. The objective of this paper is to study the electrical and mechanical characteristics of fine pitch TSV. The features are that the fine pitch TSV samples are fabricated with self-integrated micro heater and thermocouple, which are integrated to act as the hot...
Three-dimensional (3D) stacked memory module based on TSV is becoming an attractive alternative. Chips are assembled through micro bumps, which will bring additional thermo-mechanical stress, as well as the channel resistance and interconnection reliability problem. In this paper, we leverage thermal cycles to assess the mechanical and electrical reliability of a bump-less wafer-on-wafer integration...
This paper demonstrates a five layers wafer level packaging. This technology has been specially developed for chip scale atomic clock system package. It includes a sealed vapor cell and two supports for vertical-cavity surface-emitting lasers and photodetector. The sealed cavity is achieved by Glass-Silicon-Glass (G-S-G) anodic bonding with high hermeticity, high reliability and low bonding temperature...
In this paper, electrical measurement and analysis of TSV/RDL is carried out, to evaluate the fabrication process and get a comprehensive understanding of electrical properties of TSV/RDL interconnect structures. DC resistance, leakage current and high frequency characterization are implemented. TSV shows a spreading distribution of DC resistance, with minimum of 4.3 mΩ. Leakage current of TSV reaches...
In this paper, a Micro-Infrared Photo-elasticity (MIPE) system was set up and applied to evaluate the residual stress of Si chip around TSV. The MIPE system can only give overall stress information along thickness. To investigate the stress distribution around TSV quantitatively, finite element method was employed and the simulation results were compared with that of experimental measurements. Through...
In this paper, a Micro-Infrared Photo-elasticity (MIPE) system was set up and applied to evaluate the residual stress of Si chip around TSV. The MIPE system can only give overall stress information along thickness. To investigate the stress distribution around TSV quantitatively, finite element method was employed and the simulation results were compared with that of experimental measurements. Through...
In order to qualify through silicon via (TSV) structures during manufacturing effectively and efficiently, two low-frequency testing methods were proposed here for electrical property and defect diagnosis of TSV samples. The first method (Method I) based on four-point probe test was adopted to measure via resistance and contact resistance, while the second method (Method II) based on two-point probe...
In the first three quarters of 2013, semiconductor industry witnessed a great multiplication of 12-inch TSV wafers mounting to 1 million plus scale. Despite this increasing popularity, TSV technology suffers from high cost due to yield loss caused by process defects. Poor insulation and connectivity are the major problems for TSV and RDL(Re-Distribution Line) structures. Without a cost-effective test...
This paper focuses on the electrical simulation and analysis of silicon interposer. Basic interconnect elements such as TSV and RDL are simulated and verified with measurement results, electrical parameters are extracted and analyzed. Segmentation is used in long signal path modeling to improve simulation efficiency with a fine accuracy. Silicon interposer is segmented into many interconnect pieces...
We reported a wafer level through-stack-via (TSV) integration approach for stacked memory module using onetime bottom-up copper filling. This bumpless TSV integration approach simplified the fabrication process and provided better reliability compared with solder based technologies. Silicon wafer with blind vias was first bonded to a carrier wafer face to face with pre-patterned BCB, and then thinned...
In this study, a stacked SRAM module with a built-in decoder was proposed with a through-multilayer TSV integration process. The through-multilayer TSVs provided data passages for all common signals, including the address bus, data bus, power, read and write control, which were redistributed at each individual chip, while the chip select signals were connected separately to the built-in decoder. Regarding...
Metallic wafer bonding has emerged as a key technology for microelectronics and MEMS. The Si wafers with Al metallization film on surface are bonded by applying Sn film as intermediate layer, aiming at the application of heterogeneous integration. Averaged shear strength of 9.9 MPa is realized at bonding temperature as low as 280°C with bonding time as short as 3 minutes under the bonding pressure...
In this paper, a through-stack-via integration process for SRAM module was developed using wafer level pre-patterned BCB bonding. A SRAM module with a built-in decoder has been designed according to this integration process. TSVs passed through all stacked SRAM chips and common signals, including address bus, data bus, power, write and read control, were connected to the same TSV using RDL. The chip...
3D integration with TSVs (Through Silicon Via) is emerging as a promising technology for the next generation integrated circuits. Copper electroplating is one of the key technologies to fabricate TSVs. In this paper, void-free TSV filling was achieved using methanesulfonic based electrolyte and mushroom-like copper overburden was used as bumps after tin deposition. Effect of additives and current...
In this paper, a TSV last wafer level 3D integration scheme using pre-patterned benzocyclobutene (BCB) adhesive bonding was proposed. With pre-patterned BCB adhesive bonding, a one-time bottom-up TSV filling features as the last step, which eliminates the traditional solder bumping and underfill filling. Preliminary results show that this process is promising for integration of similar chips such...
Redistribution layer (RDL) is necessary for electric interconnection of TSV-based 3D stacking applications. Fabrication process and electrical measurement of RDL using benzocyclobutene(BCB) as interlayer dielectric is investigated in this paper. Photosensitive BCB and electroplating copper are applied in this process featured with low temperature below 250. Multilayered RDL has been fabricated by...
In this paper, a novel 3D integration process named Via-Backside-Release process, abbreviated as VBR process, is proposed and technical issues are addressed. With VBR process, there's no need of removal process of copper overburden due to the filling of TSV by copper electroplating, and no individual unit process for producing Cu/Sn microbumps. In order to verify the feasibility of VBR process, a...
Tapered TSV interconnection has begun used in CMOS Image Senor (CIS) and currently is penetrating its application in other areas, such as MEMS devices and Si Interposer. It helps relive the technical difficulties of conformal deposition of insulation layer and conducting layer and therefore it's helpful for yield improvement and cost reduction. Besides that, it helps also relieve the stress accumulation...
Tungsten is a promising bulk material for microsystem applications for its high melting point, radiation resistance, high strength and conductivity. In this paper, wafer level Tungsten-Glass wafer bonding was carried out with photodefinable BCB, the results were compared with Si-Glass bonding. A high-yield BCB bonding technology was developed with good uniformity and relatively high bonding strength,...
3D System in Package with Through Silicon Via has been a promising solution to enhance the integrated density[1]. However, as more and more devices are integrated in one package, the reliability and performance is affected by the work environment, such as temperature variation, vibration, drop and so on. Many researches has been done on the drop analysis of solder ball on the PCB substrate, but few...
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