The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
As CMOS technology aggressively scales down, many integrated circuits used in harsh environments such as space rely on commercial foundries to provide advanced process technologies. Designers not only need to ensure high reliability but also need to address the challenges such as the increasing variability faced by commercial applications. This paper presents a systematic foundry enhancement flow...
We propose a new physical model for deformation potential (Dac) at MOS interface. In the proposed model, Dac increases sharply near Si/SiO2 interfaces. Dac in SOI FETs with SOI thickness (TSOI) ranging from 4 to 60 nm is evaluated from Shubnikov-de Haas (SdH) oscillations. It is demonstrated, for the first time, that Dac is increased sharply at the MOS interface within a range of few nanometers; whereas...
Substrate engineering using Smart CutTM and Smart StackingTM for advanced LSIs is overviewed. For digital CMOS applications, planar fully-depleted (FD) SOI structure provides a realistic solution to bridge the technology gap between bulk CMOS and three-dimensional FD structures. Production of planar FD-SOI will be started soon in 28nm technology. RF applications, on the other hand, are the areas where...
Plasma-based surface treatment techniques such as plasma immersion ion implantation and deposition (PIII&D) is a very useful technique in the fabrication of silicon-on-insulator and high-k dielectrics and is commercially used to produce shallow junctions in deep-submicrometer integrated circuits. The applications of PIII are in fact much broader covering many other areas such as metallurgy and...
Since its discovery in 2004, graphene, a two-dimensional (2D) crystal of sp²-bonded carbon arranged in a honeycomb lattice, has rapidly emerged as an intriguing material for a broad spectrum of applications in nano-devices. Given its exceptional carrier transport characteristics, excellent thermal conductivity, and robust electro-mechanical behavior, graphene could be potentially used in applications...
A 128K-bit Low-Power SRAM with 0.2um Fully-Depleted(FD) SOI CMOS process is presented. First-cut datalO and Busr-Splitting techniques are used in the SRAM circuit design to achieve 15uA standby mode current and 20uA∼500uA active mode current after packaged in DIP28. The SRAM's Total-lonizing-Dose capability is about 20K rad(Si).
A novel 2T1C pixel circuit design for active matrix organic light emitting diodes (AM-OLEDs) based on the asynchronous double-gate low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs) is proposed and verified by SPICE simulation. First, we simulate and verify the asynchronous double-gate polycrystalline silicon thin-film transistors; then, we simulate the transient response of...
In this paper, electrical and physical characteristics of the addition of Ti into Ce2O3 dielectric films on the single crystalline silicon were studied. It can be found that the high-k Ce2Ti2O7 gate dielectrics with post rapid thermal annealing (RTA) can show higher dielectric constant, smaller gate voltage shift, higher breakdown electric field and smaller charge trapping rate.
The paper reports the design, fabrication and thermal property investigation of serpentine micro-channel structure embedded in Low Temperature Co-fired Ceramic (LTCC) substrate for thermal management of 3D micro-system. Serpentine micro-channel structure is about 2cm(length) × 2cm(width) × 2mm(thickness) in dimension and the micro-channel is about 200μm×200μm in its cross section. Infrared imaging...
Numerical simulations of grain boundaries barriers and drain current are carried out in polysilicon thin-film transistors based on discrete grain boundaries (GBs). The height of grain boundary barrier was analyzed under various biases conditions and drain induced grain barrier lowering (DIGBL) effect was observed. The influence of trap states density in GBs on current characteristics was also studied...
A new super junction (SJ) VDMOS with an extended high permittivity (HK) dielectric-filling trench is proposed. A narrow N/P column in the SJ structure can be realized by using trench technology and angled ion implantation. The assistant depletion caused by the HK dielectric increases doping concentration of the N-drift region and thus reduces the specific on-resistance (Ron, sp). Furthermore, HK dielectric...
A configurable active-RC filter for a half-duplex transceiver is presented. The filter is primarily composed of two low-pass filters (LPF), which are shared between transmitter mode and receiver mode of the half-duplex transceiver. When in transmitter mode, the filter is simply used as I/Q LPF, and in receiver mode, the filter is configured as a complex filter, with the help of a configurable switching...
A novel SJ-LDMOS using charge-balanced pillar and N− buffer layer (CBB) is proposed. The charge-balanced pillars which provide additional charges for compensating a surplus of p-type charges around the drain end insure the charge balance and eliminate the substrate assisted depletion effect. In addition, the N− buffer layer under SJ region enables CBB SJ-LDMOS to use shallow pillars. Therefore the...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.