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As the electronics production at China continuously growing, the semiconductor chip consumption already exceeds 50% of global total since 2012. This attracts investment of wafer Fab's as well as advanced technologies development at China from both domestic and international partners. In turn, all semiconductor manufacturing related development and services (i.e. tools, materials, packaging, testing,...
We systematically analyzed that the "dark-gate" defects were detected by e-beam and bright field inspection as one of the top yield limiters (i.e. the defects of gate-to-contact shorts/leakage) and correlated these to physical failure modes in multiple steps through RMG and MOL process steps. A few effective/novel solutions in the process steps are successfully demonstrated with planar CMOS...
As dimension of middle-of-line contacts scale down, the Tungsten (W) gap-fill capability is critical, and we started to see function failure in SRAM and logic circuit caused by W-voids. We had observed that formation of W-voids is related to the contact profile, nucleation/barrier on sidewall, and deposition methods. Furthermore, even those initially “good” W-plugs are formed, the subsequent process...
The FinFET technology is continuously progressing toward 14nm node on SOI and bulk substrate with good compatibility with planar CMOS and driving CMOS scaling and Moore's law for low-power/SOC and future Internet-of-Things (IOT) applications. The challenges of new FinFET technology in manufacturing at 14nm and beyond is reviewed.
As dimension of middle-of-line contacts scale down, the Tungsten (W) gap-fill capability is critical, and we starts to see function failure in SRAM and logic circuit caused by W-voids. We had observed that formation of W-voids is related to the contact profile, nucleation/barrier on sidewall, and deposition methods. Furthermore, even those initially "good" W-plugs are formed, the subsequent...
We systematically analyzed that the "dark gate" defects were detected by bright field inspection and e-beam as one of the top yield limiters (i.e. the defects of gate-to-contact shorts/leakage) and correlated to physical failure modes in multiple steps through RMG and MOL process steps. A few effective/novel solutions in process steps are successfully demonstrated with planar CMOS technology,...
As CMOS scaling continuous successfully, technologies for integrating both memory and logic together is highly desirable for high performance and low-power system-on-chip (SOC) with full CMOS compatibility, such as Logic based NVM, floating-body DRAM, MiM based eDRAM, PC-RAM, RRAM, MRAM, FeRAM, ...etc.. New materials (e.g. GST, metal-oxide, high-k, magnetic junction, ...etc.) have greater compatibility...
Several recent studies of power MOSFETs are discussed in this paper: (a) The second-breakdown of power MOSFETs is shown to be triggered by the turn-on of the parasitic bipolar transistor, (b) The I-V characteristics of power MOSFETs operating in reverse mode (such as when used as a synchronous rectifier) are studied, (c) A H5°-spreadingangle model for the calculation of epi-resistance is shown to...
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