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In this paper, the 32-channel readout front-end device with a Bluetooth 2.0 module and a MSP430 ultra-low power microcontroller for portable Electroencephalograph (EEG) acquisition is presented. In addition to the consideration of low power, low noise, and high efficient chip area usage, the extendable readout front-end chip is presented with a design of chopper-stabilized differential difference...
This paper proposes an extendable front-end readout chip (EFRC) for electroencephalography (EEG) measurements. An EFRC is developed for EEG measurement with features including low power consumption, a high signal-to-noise ratio, and highly efficient chip area usage. A chopper-stabilized differential difference amplifier (CHDDA) is used in the first stage to amplify signals and then during another...
This paper presents a steady-state visually evoked potential (SSEVP) EEG-based brain-computer interface (BCI) with real-time artifact removal using independent component analysis (ICA). This system comprises an SSEVP-based stimulator, a four-channel electroencephalogram (EEG) front-end module, an ICA-based artifact removal module, and a canonical correlation analysis (CCA) detection module. The proposed...
E-book readers have the inherent advantage of affording learners both mobility and convenience. They can be considered ideal pedagogical tools for supporting learners¡¦ reading activities. In this study, the reading strategies SQ3R (Survey, Question, Read, Recite and Review) with the guidance mechanism were integrated into the e-book reading environment for assisting learners in their reading processes...
This paper presents a brain-computer interface with real-time independent component analysis for biomedical applications. EEG-based BCI technology using cell-phone and Bluetooth transmission of bio-signals has been established in previous studies, and experimental results show that subjects should avoid eye blink who are under test to increase the accuracy. In order to enhance the dialing system,...
In this paper, a highly-integrated multiprocessor chip design enabling the real-time processing of biomedical signals in portable brain-heart monitoring systems is presented. The architecture comprises a novel diffuse optical tomography (DOT) processor for taking brain imaging, an independent component analysis (ICA) processor for removing artifacts of brain electroencephalogram (EEG) signals, and...
This paper presents a low-power VLSI implementation of a 4-channel independent component analysis (ICA) processor for portable EEG signal processing applications. The low-power scheme employed for this ICA chip is based on power gating and clock gating by utilizing Cadence common power flow (CPF) low-power methodology and also according to the characteristics of ICA training behavior using different...
In this paper, a low noise and robust test scheme for 3D stacked integrated circuits based on modified standard IEEE 1149.4 has been proposed. Through the modified standard, this novel test scheme can be more robust to fulfill the microsystem integration requirements. This test scheme also makes the analog pins more observable and testable during and after the integration. The proposed test scheme...
In this paper, a low power and low noise eight-channel analog front-end (AFE) IC for portable brain-heart monitoring applications is presented. The developed IC features a fully integrated eight-channel design which includes one channel for diffuse optical tomography (DOT), three channels for electrocardiography (ECG), and four channels for electroencephalography (EEG). In order to achieve the targets...
In this paper, a new design for efficiency enhance switching-capacitor DC-DC voltage converter based on combination of traditional charge-transfer-switch charge pump and cross-coupled output stage. In order to get a high output power and pump-efficiency. By using multi-phase technique, its can increase both of pump-efficiency and power-efficiency. The propose multi-phase mixed-structure charge pump...
In this paper, a novel low-power high-efficiency switching-capacitor DC-DC voltage converter based on the combination of static CTS (Charge-Transfer-switch) charge pump and cross-coupled charge pump is presented. At this time, some motivated methods to overcome both the reverse charge sharing problem of traditional static CTS charge pump and the problem of threshold drop at the output stage are proposed...
An enhanced high-efficiency switching-capacitor DC-DC voltage converter based on the combination of charge transfer switch (CTS) charge pump and cross-coupled output stage is presented. Some motivated methods to overcome the reverse charge sharing problem of traditional CTS charge pump are discussed and a new mixed structure is proposed to conquer the remaining problem of threshold drop at the output...
This paper describes a novel charge pumping technique for low-power dc-dc converters by switched capacitors. The proposed configurations were based on the charge-transfer-switch (CTS) topology. In this paper, the problems and possible solutions for conventional static CTS charge pumps will be surveyed. In our study, a novel static CMOS voltage shifter which was called the voltage level controller...
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