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Energy consumption has become the major concern of the IC industry. As a result, near-threshold-voltage (NTV) design has attracted a lot of attention for its superiority in energy efficiency. However, NTV design is faced with the key challenge — variability, especially for FinFET technology where device electrical FoMs are found to be strongly correlated. In this paper, new methodology of NTV design...
A new static power clamp circuit integrated with input ESD protection is proposed in this paper. By skillfully incorporating traditional input ESD protection, the proposed circuit replaces the protection resistor by the active switch and merging the signal control circuit into trigger circuit of static power clamp. The proposed circuit is a whole-chip ESD protection scheme that has a low leakage and...
A new reliable Electrostatic Discharge (ESD) power-rail clamp circuit has been proposed in this paper. The new circuit structure has achieved good results in reducing leakage current, anti-false triggering, increasing discharge transistor's turn on time. During the ESD event, the proposed circuit has a discharge time of 755.22ns, which is about 6.74 times that of conventional R-C power-rail clamp...
The analysis of self-heating effect in a SOI LDMOS device under an ESD stress is presented in this paper. TCAD tools are used as the platform to explore the physical process of the bulk LDMOS device and the influence of buried oxide layer inserted in the substrate. Simulation results uncover that the buried oxide layer degrades the current-handling ability and changes the lattice temperature distribution...
In this work, we investigated the influence of retrograde-well implantation on hetero-structure body-tied germanium (Ge) FinFET [1]. Using structural engineering, the retrograde well was fabricated prior to Ge epitaxy, which could avoid the activated temperature of dopant in Si substrate. With optimizing the implant condition, the p-Ge/n-Si hetero-structure junction exhibited high ION/IOFF ratio and...
This work presents a novel power-rail electrostatic discharge (ESD) clamp circuit for nanoscale applications. By skillfully incorporating transient and static ESD detection mechanisms into its detection circuit, the proposed circuit achieves a wide range of adjustable triggering voltage (Ft1) while maintaining low standby leakage current (Ileak). Besides, the proposed circuit achieves significantly-improved...
N-type InGaAs MOSFETs with self-aligned nickel-InGaAs alloy and ex-situ ALD Al2O3 as gate dielectrics was successfully fabricated. The InGaAs MOSFETs exhibit an S/D resistance (Rsd) that is lower than that in P-N junction devices due to the low Schottky barrier height and the peak mobility was about 1138 cm2/V-s and the interface state density (Dit) was about 1012 cm−2eV−1 at Et = Ev + 0.6 eV by using...
Double snapback phenomena in transient power-rail ESD clamp circuits are reported in this paper. By properly sequencing different snapback mechanisms, the reported double snapback phenomena present latch-up free ESD protection schemes. Experiment results verify that both the first holding voltage (Vh1) and second holding current (Ih2) meet latch-up free criteria for the utilized 65-nm CMOS process...
In this work, new design techniques that aim to reduce power consumption of true single-phase clock-based (TSPC) prescalers is presented. The structure of divide-by-4/5 frequency divider is simplified, and its performance is compared with previous work to demonstrate the improvement. Simulation results show at least a 25% reduction of power consumption is achieved by the proposed unit. In the 32/33...
A novel multi-RC-triggered power clamp circuit is proposed in this paper. Effective capacitances of capacitors are multiplied by current mirrors and a modified asymmetric phase inverter is employed in the proposed circuit. Simulation and test results verify that the proposed circuit maintains enhanced ESD protection robustness with reduced chip-area.
In this study, the electrical characteristics of high-k Tb2O3 polyoxide capacitors combined with rapid thermal post annealing have been improved (i.e.lower leakage current, higher electrical breakdown filed and lower electron trapping rate). The post-RTA annealing treatment can passivate and reduce trap states to terminate dangling bonds and traps in the high-k Tb2O3 dielectric and the interface between...
A novel LDMOS-SCR device for electrostatic discharge protection of power device is presented. The device is able to be fabricated in SOI 40V LDMOS process without any extra mask. Due to the new structure, a proper and controllable triggering voltage and fine heat dissipation capability are achieved.
In this paper, we design and implement a hybrid WiMAX network testbed that integrates the NCTUns network emulator with a real-life WiMAX network. This hybrid WiMAX network testbed can seamlessly connect virtual networks (emulated by NCTUns) to a real-life WiMAX network. Thus, in this testbed real-life applications on real machines can exchange data with those on emulated (virtualized) network nodes...
This paper proposes a method aiding in low clock skew applicable to the mainstream industry clock tree synthesis (CTS) design flow. The original clock root is partitioned into several pseudo clock sources at the gate level. The automatic place and route (APR) tool may synthesize the clock tree with better performance in clock skew because each pseudo clock source drives smaller number of fan out....
Dynamic circuit is suitable for high-speed application, but often suffers from noise related reliability problems which become increasingly prominent as the technology are entering into the scores of nano meter era. This paper presented a new dynamic circuit scheme, which could achieve higher noise margin without sacrificing much power consumption and delay time. This design achieves a higher noise...
This paper proposes a ZSCTS methodology aiding in zero skew clock tree synthesis suitable to the mainstream industry clock tree synthesis (CTS) design flow. At the gate level, the original clock net is broken up into smaller partitions, and the clock buffers are inserted as pseudo clock sources to drive each portion. The automatic place and route (APR) tool may synthesize each clock subtree with better...
An efficient encoding scheme is proposed for folding ADC. In the encoder, XOR-OR encoding algorithm and dynamic domino circuit are adopted. A novel method for wide-range error correction and bit synchronization is presented. Simulation results show that the proposed encoder has several advantages: high speed, low power dissipation and small chip area.
In this paper, a high performance tiny grain polycrystalline pentacene OTFT were produced by introducing a polymethylmethacrylate (PMMA) insulator as a gate dielectric modification layer. A typical bottom gate configuration with a silver top contact OTFT to study the electrical characteristics, charge transport properties, and the hysteresis or memory effects in the current-voltage characteristics...
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