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This paper describes a non-binary SAR ADC architecture that is reconfigurable at production testing time to increase the number of chips that meet a given sampling speed specification, i.e. to improve yield. A non-binary SAR ADC can realize higher sampling rates than a comparable conventional binary SAR ADC, by using overlapping SA ranges so that any errors due to incomplete settling of the internal...
This paper presents a 0.45V-to-2.7V level shifter utilizing inductive coupling. Since primary and secondary coils are AC-coupled, each coil can be biased at arbitrary voltage independent from the conversion level difference. This enables both the primary and the secondary circuits to operate at the optimal operating region. In addition, the inductive coupling itself can provide an additional intermediate...
MuCCRA-cube is a scalable three dimensional dynamically reconfigurable processor. By stacking multiple dies connected with inductive-coupling links, the number of PE array can be increased so that the required performance is achieved. A prototype chip with 90 nm CMOS process consisting of four dies each of which has a 4 times 4 PE array was implemented. The vertical link achieved 7.2Gb/s/chip, and...
This paper presents a three-dimensional (3D) system integration of a commercial processor and a memory by using inductive coupling. A 90 nm CMOS 8-core processor, back-grinded to a thickness of 50 mum, is mounted face down on a package by C4 bump. A 65 nm CMOS 1 MB SRAM of the same thickness is glued on it face up, and the power is provided by conventional wire-bonding. The two chips under different...
This paper presents a novel impulse radio based ultra-wideband transmitter. The transmitter is designed in 0.18 mum CMOS process realizing extremely low complexity and low power. It exploits the 6-to-10 GHz band to generate short duration bi-phase modulated UWB pulses with a center frequency of 8 GHz. No additional RF filtering circuits are required since the pulse generator circuit itself has the...
This paper discusses a low-power inductive-coupling link in 90 nm CMOS. The novel transmitter circuit using charge recycling technique for power-aware three-dimensional (3D) system integration is proposed and investigated. Cross-type daisy chain enables charge recycling and achieves power reduction while keeping communication performance such as high timing margin, low bit error rate and high bandwidth...
A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30mum. The total layout area is 2mm2 in 0.18mum CMOS and the chip thickness is 10mum. 4-phase TDMA reduces crosstalk and the BER is <10minus;12. Bi-phase modulation is used to improve noise immunity, reducing...
This paper discusses a daisy chain of current-drive transmitters in inductive-coupling CMOS links. Current is reused by multiple transmitters. 8 transceivers are arranged with a pitch of 20mum in 0.18mum CMOS. Transmit power is saved by 35% without sacrificing data rate (1Gb/s/ch) and BER (<10-12) by having 4 transmitters daisy chained
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