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The reliability of FPGA based hardware designs has become an important field of research particularly for space computing. Traditionally, redundancy is utilized in FPGA based designs to achieve reliable or error-tolerant computing. However, the redundant designs vary according to the granularity level and the voter placement algorithms used for the hardware design. The resulting circuit configurations...
The reliability of FPGA based hardware designs has become an important field of research particularly for space computing. Traditionally, redundancy is utilized in FPGA based designs to achieve reliable or error-tolerant computing. However, the redundant designs vary according to the granularity level and the voter placement algorithms used for the hardware design. The resulting circuit configurations...
With increasing error-proneness of nano-circuits, a number of fault-tolerance approaches are presented in the literature to enhance circuit reliability. The evaluation of the effectiveness of fault-tolerant circuit structures remains a challenge. An analytical model is required to provide exact figures of reliability of a circuit design, to be able to locate error-sensitive parts of the circuit as...
With ever-decreasing CMOS transistor sizes, integrated circuits are becoming more and more susceptible to errors. A commonly used approach to improve the reliability of digital circuits is triple modular redundancy (TMR). TMR instantiates three copies of a circuit plus additional voter circuits to take majority decisions on the output values. Prior research has studied variations in TMR voting structures...
The reliability of FPGA based hardware designs is becoming a challenge with future device technologies and, in particular, for avionic and space applications where FPGAs might get exposed to high radiation levels. Typically, redundancy-based techniques are used to achieve fault-tolerant operation. However, hardware redundancy comes with an overhead in performance factors such as area requirement,...
The error-sensitivity of nanoscale circuits is an extremely important issue in electronic industry these days. The reason is the high susceptibility of electronic circuits to noise at the nanoscale level. Markov Random Field (MRF) modelling is one approach to achieve noise-tolerance in integrated circuit design. In this paper, we have designed an error-detection mechanism for digital circuits based...
A novel, improved and economical approach for a universal voltage source sine-wave inverter is presented in this paper. Existing inverters methodologies with sine-wave output are expensive and sometime go beyond the budget for home application. Common drawbacks associated with existing low cost inverters are square-wave output, bulky size, noisy output voltage and poor efficiency. In addition to that,...
Scaling of CMOS technology is degrading the reliability of upcoming microelectronic devices. When the circuit design enters the nanoscale dimensions, the inputs have more influence on the circuit's reliability due to the circuit's internal noises and gate errors. In this paper, we will model the deterministic inputs probabilistically and analyze their effect on the reliability of digital circuits...
The reliability of digital circuits is greatly distorted as the VLSI design cycle enters into nanoscale arena. In the past, the inputs of digital circuits were considered deterministic but shifting of transistor technology into nanoscale dimensions has made their behaviour totally probabilistic. The reason is that logic level voltages suffer from a number of fluctuations due to the effect of signal...
The reliability is one of the serious issues confronted by microelectronics industry as feature sizes scale down to nano-design level. In this paper, we are providing the analysis to find the accurate and efficient method of finding circuit's reliability among the available options. The experimental results provide the reliability evaluation of few probabilistic computation schemes. The comparison...
The reliability of digital circuits is in question since the new scaled transistor technologies continue to emerge. The major factor deteriorating the circuit performance is the random and dynamic nature of errors encountered during its operation. Output-error probability is the direct measure of circuit's reliability. Bayesian networks error modeling is the approach used to compute error probability...
Fault-tolerance in integrated circuit design has become an alarming issue for circuit designers and semiconductor industries wishing to downscale transistor dimensions to their utmost. The motivation to conduct research on fault-tolerant design is backed by the observation that the noise which was ineffective in the large-dimension circuits is expected to cause a significant downgraded performance...
Current trend of downscaling CMOS transistor dimensions is increasing the liability of digital circuits to be easily affected by noise. The resulting unexpected behaviour of our digital devices is due to the low supply voltage of these downscaled circuit elements. Though the low supply voltage decreases the power dissipation of a circuit to a great extent, it decreases the signal to noise ratio as...
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