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In this paper, we investigate the geometry dependence for the local variation of low-frequency noise in MOSFETs via the sum of lognormal random variables. A compact model has been developed and applied to the measured data with excellent match, and therefore enables the coverage of low-frequency noise statistics in circuit design.
We present device and circuit characterization resulting from technology/design co-development to improve the design and manufacture of analog/mixed-signal (AMS) circuits in processors. We introduce ID-based MOSFET transconductance measurements and a new measurement of drain saturation margin at realistic analog biasing. We also describe routinely monitored scribe lane replicas of key AMS passives...
On-chip inductors are recently in high demand even for digital applications due to strict jitter and phase noise requirements in oscillators. Accurate and fast modeling techniques are needed to enable low-cost and fast silicon turnaround. We present a fast and accurate methodology named scaled, iterative, and sampled (SIS) non-linear least squares optimization to extract wide-band model parameters...
Off-state leakage current in a 65 nm partially depleted (PD) floating-body (FB) SOI technology is modeled and analyzed with emphasis on its drain-voltage dependence. Modeling accuracy of the off-state leakage current is highly dependent on modeling of parasitic currents, although their direct contribution to the leakage may be negligible in lower-power/high-performance technologies. The underlying...
Critical currents (ICRIT) extracted from the N-curves of a 6-T SRAM bit cell have been shown in recent research to be important and effective figures of merit for the cell??s stability and write-ability. SPICE models of cell transistors, therefore, not only need to fit closely to individual transistor??s I-V characteristics, but also faithfully reproduce ICRITs?? behavior of the cell as a whole. A...
Speculative SPICE models (also referred to as evaluation-level or guess models), which are extracted based on projected device electrical characteristics (called `targets??) rather than actual measurement data, are required to support concurrent IC designs. The self-heating effect in silicon-on-insulator (SOI) technologies presents additional challenges in obtaining quality speculative SOI MOSFET...
This paper reviews the status and challenges of the modeling partially-depleted silicon-on-insulator transistors. Many challenges stem from the floating-body potential, which offers advantages in terms of performance and leakage, but presents complex electrical behavior. Circuit simulator considerations and the importance of model standardization are also highlighted.
Logic performance is improved by creating more stress in the channel in advanced CMOS technologies. Impact of stress on different circuit blocks in a microprocessor chip has not been studied in detail. This paper presents a comprehensive study on the effects of stress and the corresponding process steps on various circuit characteristics. Analog behavior, hysteresis and noise properties are investigated...
Logic performance is improved by creating more stress in the channel in advanced CMOS technologies. Impact of stress on different circuit blocks in a microprocessor chip has not been studied in detail. This paper presents a comprehensive study on the effects of stress and the corresponding process steps on various circuit characteristics. Analog behavior, hysteresis and noise properties are investigated...
A new methodology is proposed to extract self-heating free I-V curves, including the substrate current, of SOI MOSFETs based on triple-temperature, regular DC measurement. It is verified to be accurate with Hspice simulations and suitable for SPICE model parameter extraction. It is also demonstrated that extraction of self-heating free I-V curves is not only desired for efficient SPICE model generation,...
As we scale down to sub-65nm technologies, transistors and interconnects no longer act as predictable elements, but start acting as statistical blocks due to static and dynamic variations. This invited paper first reviews some of the key variations that need to be considered for any statistical analysis. Also, details for implementing statistical models into compact modeling flow are discussed. Finally,...
An anomalous behavior of nMOSFET's hot carrier reliability characteristics has been investigated at an elevated temperature for the first time. Although the degradation of linear drain current is significantly reduced with increasing stress temperature, the degradation of saturation drain current is enhanced for high temperature stress. This behavior can be explained by the reduction of the velocity...
An anomalous behavior of nMOSFET's hot carrier reliability characteristics has been investigated at an elevated temperature for the first time. Although the degradation of linear drain current is significantly reduced with increasing stress temperature, the degradation of saturation drain current is enhanced for high temperature stress. This behavior can be explained by the reduction of the velocity...
In this paper, an anomalous temperature dependence of hot carrier lifetime has been extensively studied for the first time. We have found that the hot carrier lifetime does not increase linearly with increasing stress temperature. On the contrary, around 90??C, hot carrier lifetime decreases with increasing stress temperature. Using the charge pumping method, we found that interface state distribution...
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