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We present an 8.0-Gb/s HyperTransport™ technology I/O built in a 32-nm SOI-CMOS processor for high-performance servers. Based on a 45-nm design that caps at 6.4 Gb/s, the 32-nm transceiver achieves up to 8.0 Gb/s over long-reach board channels. Key enhancements include a high-bandwidth (>200 MHz) PLL to attenuate high-frequency jitter in the received forwarded clock and redesigned power-hungry...
On-chip inductors are recently in high demand even for digital applications due to strict jitter and phase noise requirements in oscillators. Accurate and fast modeling techniques are needed to enable low-cost and fast silicon turnaround. We present a fast and accurate methodology named scaled, iterative, and sampled (SIS) non-linear least squares optimization to extract wide-band model parameters...
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