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This work investigates the calibration procedure of a conventional relaxation oscillator. First, the numerical analysis is performed in MATLAB in order to evaluate the sensitivity of the procedure to the noise generated inside the chip and measurement system. Next, the theory is experimentally verified by calibrating four test chip samples designed and manufactured in 0.35-µm CMOS technology. The...
This paper presents an improved technique for the calibration of the relaxation oscillators with respect to the delay of the comparators. The drawbacks of the conventional topology for the relaxation oscillators are analyzed. Based on the analysis, the circuit modification which resolves the effects of the comparator delay in the trimming procedure is proposed. The simulations in ams 0.18μ CMOS technology...
This work shows for the first time the presence of erratic phenomena in p-channel floating gate memories using Fowler Nordheim tunneling for both program and erase operations. A specific p-channel EEPROM architecture is investigated and found to be intrinsically robust against erratic behaviors. A comparison between the p-channel device and a conventional n-channel Flash is discussed and physical...
Qualifying a high temperature, high endurance and high reliability integrated EEPROM process module according the JEDEC and AEC standard needs a large number of tested devices. Correlations of various analog and digital measurements must be done at different supply voltages, temperature conditions and with process variations to ensure a stable high yielding process module. Long program and erase times...
Summary Integration of low voltage analog and logic circuits as well as high-voltage (HV) devices for operation at greater than 5 V enables Smart Power ICs used in almost any system that contains electronics. HVCMOS (High-Voltage CMOS) technologies offer much lower process cost, if compared to BCD technologies, they enable multiple HV levels on a single chip, and need less effort when scaling to smaller...
The existing embedded nonvolatile memory technologies have failed to deliver a cost effective solution for SoC applications. The major reason has been that most of these technologies were not designed specifically for the embedded applications. There have been two approaches for the embedded nonvolatile memories. One is to take the high density stand alone memory technology and use it for embedded...
A highly reliable and scalable non-volatile embedded memory cell and technology is described. This embedded technology operates at very low power, and has minimal impact on the analog and digital components used in the SoC design. The main objective of this technology development was to achieve high reliability and high data retention for automotive applications over the extended temperature range...
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