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A kinetic model was proposed to describe hyperbranched polymers (HBPs) formed by the polymerization of monomers A2 and B3 with monofunctional compound (BR) added gradually in a semibatch reactor. The dependences of the degree of polymerization (DP) and the degree of branching on the reaction time and the monomer compositions were calculated. The DP of the HBPs could be increased by the slow addition...
This paper represents a layout solution to reduce the on-chip couplings in between two BALUNs, which is implemented by UMC 28iim CMOS process. In advanced CMOS technology and circuit application applied for higher frequency, couplings are always an issue to be solved, which are mostly coming through substrate, magnetic fields or electric fields. A floating ring is in use to block the magnetic couplings...
A 2.4/5GHz Fully-Integrated Transceiver is implemented in 65nm CMOS technology. To alleviate the cost of external front-end components, the G-mode RF transmit/receive (T/R) switch and a power-efficient linear CMOS PA are fully integrated on-chip. On the other hand, for better performance, only the A-mode PA is integrated on-chip while the external T/R switch is used. It shows 5dB and 5.5dB NF in the...
A 2.4 GHz linear CMOS power amplifier (PA) for OFDM WLAN application in 65 nm CMOS technology is presented. The cascode PA operating from 3.3 V employs the proposed asymmetric lightly doped drain MOSFET (A-LDD) structure as common-gate stage to sustain large signal stress and 1.2 V core device as common source stage to provide high frequency operation. Beside, dynamic bias technique is used not only...
This study demonstrates an RF active device based on A-LDD (asymmetric lightly doped drain) MOSFET structure which has higher drain to gate and drain to source breakdown voltage due to removing LDD and halo doped region from the drain side. It is suitable to be used in RF PA (power amplifier) design for SoC (system on chip) in advance 65 nm node and below technology. The manufacturing of A-LDD MOSFET...
A 2.4 GHz fully-integrated MISO transceiver consisting of two receivers and one transmitter is implemented in 0.18 mum CMOS technology. To alleviate the cost of external front-end components, the RF transmit/receive (T/R) switch and a power-efficient linear CMOS PA are fully integrated on-chip. It shows 3.5 dB low noise figures in the receivers respectively. Also, the transmitter delivers an average...
A fully integrated transmitter front end with on-chip power amplifier (PA) in 0.18 um CMOS technology is presented. The on-chip PA employs dynamic bias technique to reduce power consumption and enhance linearity. In the measurement, it reveals the output PldB of the PA is 26.5 dBm. Also, the transmitter delivers an average power of 17.3 dBm with EVM of -28.1 while drawing 225 mA of DC current (PA...
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