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This paper describes a byte alterable EEPROM with B4-HE (Back-Bias assisted Band-to-Band tunneling Hot-Electron injection) architecture employing three-transistor of AND-type unit cell for disturb-free operation. B4-EEPROM cell array has been fabricated using a 90nm flash process, and single-pulse program and erasure cycling has been confirmed up to one million, with keeping programming time of 10us...
This paper describes a true 6F2 B4-Flash (Back Bias assisted Band-to-Band tunneling induced Hot Electron injection Flash) memory cell, which is one half of conventional NOR cell, for the first time as a floating gate NOR cell. 6F2 B4-Flash cells featuring a self-aligned STI and self aligned contact architectures have been fabricated by a 90nm process and was confirmed sufficient performance for NOR...
This paper describes a 90nm Logic NVM "eCFlash", which can be embedded in standard CMOS process without any mask adder and any process modification. In the eCFlash element, the charge is stored in the side spacer region of CMOS transistor, consequently its charge loss process is not influenced by the leakage current through the gate oxide and surface leakage current on the side spacer, which...
This paper introduces a first 512Mb B4-Flash product chip with 8F2 cell size, which is the smallest NOR cell in the 90nm generation. High rewriting throughput (∼8MB/s) is realized by 10MB/s programming and 100ms/block erasing without over-erase problem. 10MB/s programming is achieved by 1kB simultaneous programming and proposed fast verify scheme. This work proves that B4-Flash can realize not only...
We propose a simple multi-degree ROADM architecture based on a massive port count WSS with integrated colorless ports. We create a simple multi-ring network and demonstrate the multi-degree colorless ROADM.
A 128times128 3D-MEMS optical switch module has been developed. A prototype switch module enables the simultaneous switching of all optical paths. The insertion loss is less than 4.8 dB and 2.6 dB on average. Regarding environmental characteristics, we confirmed that the module operates flawlessly when temperature in the installation room changes from -5 to 50degC. We also confirmed that the switching...
A 90 nm floating gate NOR B4-Flash memory with IF (F: minimum feature size) gate length cell has been investigated by using 64 Mbit test chip to evaluate the scalability of B4-Flash memory. 90 nm (=1F) gate length of memory cell is shortest in many NOR flash memories reported previously. Basic program and erase characteristics and robust program disturb immunity of B4-Flash memory utilizing NMOS select...
This paper describes the reliability characteristics evaluation results of floating gate type B4-flash (back bias assisted band-to-band tunneling induced hot electron injection flash) with statistics. Data retention reliability of B4-flash with N+gate and P-channel memory cell utilizing B4-HE program and FN channel erase is evaluated extensively under bake temperature of -24C to 250 C up to 7000hrs...
A new logic NVM "eCFlash (embedded CMOS Flash)" has been developed without any additional process steps in a 0.25 um technology. In this architecture, a novel differential sense-latch cell with charge-trapping storage is adopted. This unique cell structure functions as a differential sense amplifier as well as a data latch, therefore mass data can be restored to each cell's latch simultaneously...
This paper demonstrates that B4-HE injection programming scheme can be easily evolved to a floating gate cell. By applying a moderate back bias to the cell during programming, the bit-line voltage can be reduced below the supply voltage, 1.8 V. As a result, B4-flash can achieves high speed programming comparable to conventional NOR and high programming efficiency comparable to NAND flash at the same...
A 1.8V 4 Mb floating-gate flash test chip utilizing back bias assisted band-to-band tunneling induced hot electron (B4-HE) injection mechanism (B4-Flash) has been fabricated. Double source line architecture (DSLA) and selective verifying method (SVM), applied to NOR arrayed B4-Flash enables to achieve 100 MB/s programming speed. The MLC capability of B4-Flash memory is also shown by realizing three...
In this paper, efficient optimization techniques are used to solve multi-objective optimization problems arising from Simulated Moving Bed (8MB) processes. SMBs are widely used in many industrial separations of chemical products and they are very challenging from the optimization point of view. With the help of interactive multi-objective optimization, several conflicting objectives can be considered...
A high-speed, small-area DRAM sense amplifier with a threshold-voltage (VT) mismatch compensation function is proposed. This sense amplifier features a unique hierarchy data-line architecture with a direct sensing scheme which uses only nMOS transistors in the array, and a simple VT mismatch compensation circuitry which uses a pair of nMOS switching transistors. The layout area of the sense amplifier...
Alternatives for on-chip voltage limiters and direct sensing schemes were evaluated in terms of ease of design, voltage margins and speed. Based on these evaluations, a 0.3??m ECL 4Mb BiCMOS DRAM was designed with a simulated access time of 7.8ns. It incorporates a voltage limiter featuring connection to VCC terminals, a BiCMOS output stage and use of a band-gap reference scheme, and a direct sensing...
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