This paper describes a byte alterable EEPROM with B4-HE (Back-Bias assisted Band-to-Band tunneling Hot-Electron injection) architecture employing three-transistor of AND-type unit cell for disturb-free operation. B4-EEPROM cell array has been fabricated using a 90nm flash process, and single-pulse program and erasure cycling has been confirmed up to one million, with keeping programming time of 10us and erase time of 1ms. It is demonstrated that the excellent capability of more than 10 years data retention at 150C. In addition, a fully designed 90nm B4-EEPROM macro specification has been investigated, and the unit cell size can be designed 57F2, which is a half those of conventional EEPROM cell size of 80-100F2.