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This paper presents a time-to-digital converter (TDC) architecture with reduced hardware suitable for multichannel timing built-out self-test (BOST) implementation on an FPGA chip. In order to reduce the number of buffers and DFFs in a conventional Flash TDC or Vernier TDC, successive approximation is applied to construct a SAR TDC when two timing inputs are repetitive (not shingle-shot). Besides,...
This paper presents a time-to-digital converter (TDC) architecture to measure the timing difference between single-event two pulses with fine time resolution. Its features are as follows: (i) The architecture is based on stochastic process and statistics theory. (ii) It exploiting the stochastic variation in CMOS process for fine time resolution so that MOSFETs with minimum sizes are utilized. (iii)...
This paper describes how using a phase switching technique can produce a low distortion signal from an Arbitrary Waveform Generator (AWG), and how this technique aligns the performance of the AWGs between testers, to evaluate the Total Harmonic Distortion (THD) performance of Analogue-to-Digital Converters (ADCs). Once a device has been characterized and correlated to the bench, the test engineer...
This paper discusses a theoretical issue of a sampling circuit to maximize SNR while keeping its bandwidth constant, in order to realize a wideband large dynamic range sampling circuit for communication system and measuring instrument applications. We consider two time-constants τ1, τ2 in the sampling circuit, where is a product of (signal source internal impedance + sampling switch on-resistance)...
This paper proposes a switching algorithm using magic square properties to improve the linearity of a unary DAC by canceling random and systematic mismatch effects among unit current (or capacitor) cells. Simulation results and discussions are provided for DAC linearity comparison in case that the proposed magic square and conventional algorithms are used.
This paper presents analysis of sampling circuit for high-frequency and high-precision waveform acquisition. We have analyzed effects finite aperture time, and we have shown derived formula for the bandwidth limitation due to its low-pass filter effects. We have checked that our theoretical calculation and SPICE simulation results agree well. We also have focused on the trade-off among bandwidth,...
This paper proposes a new ripple controlled switching converter and a new spread spectrum technique for EMI reduction. The new ripple controlled converter includes a Hip-Hop after the output of the comparator. The new spread spectrum technique uses a PLL circuit modulated by pseudo analog noise. The PLL circuit modulates a reference clock with non-periodic analog noise. This modulated clock is provided...
This paper proposes the method of automatic design of doubly-terminated RC polyphase filter by distributed genetic algorithm. Designing doubly-terminated RC poly phase filter is generally difficult due to complexity of design theory. From simulation results, we found we can design RC poly phase filter terminated at the value of 1[Ω] at both ends by automatic design.
This paper describes a design algorithm of a 2nd-order RC polyphase filter to obtain its flat passband gain. The condition for its solution is shown and the image rejection ratio formula is also derived. Its effectiveness is demonstrated by numerical calculation in several cases.
This paper describes analysis and simulation verification of a high-frequency low-distortion signal generation method with an arbitrary waveform generator (AWG). Our previously proposed phase-switching method was limited to low-distortion but low-frequency signal generation, and therefore it cannot be used directly for high-frequency signal generation. We propose here a method for generating a low-distortion...
This paper proposes the method of automatic design that satisfies desired specification of comparator circuit using the distributed genetic algorithm and the HSPICE optimization function. Since HSPICE optimization function depends on initial values, appropriate initial values are very important. Therefore, by using the distributed genetic algorithm, determining the appropriate initial value and performing...
A Single-Inductor Multi-Output (SIMO) DC-DC converter can generate various supply voltages with one inductor which can realize small size. Zero Voltage Switching (ZVS) can reduce switching loss which leads to high efficiency. In this paper, we propose a Single-Inductor Dual-Output (SIDO) boost converter with ZVS-PWM control and we show its simulation results; switching loss is reduced by 78%. Next,...
This paper proposes a novel EMI spread spectrum technique to enable to set notch frequencies using pulse modulation in switching converters. The notches appear at the frequencies obtained from empirically derived equations with the proposed spread spectrum technique using the pulse coding methods, the PWM (Pulse Width Modulation) coding or the PCM (Pulse Code Modulation) coding. This technique would...
This paper describes two linearity enhancement algorithms for I-Q signal generation using a multi-bit complex band-pass (BP) ΔΣ DA modulator targeted for communication IC design and testing applications. The first one is a complex multi-band-pass data-weighted-averaging algorithm and the second is a self-calibration algorithm. The generated I, Q signals can be up-converted to a high frequency signal...
In this paper, we propose a Hot Carrier Injection (HCI) induced gate leakage current model used for reliability simulations in 90nm n-channel MOSFETs (n-MOSFETs). As far as we have investigated, existing papers and reports regarding on HCI degradation model equations are based on the substrate current induced by the impact ionization effect. These degradation models cannot be applied for any circuit...
This paper reports a maximum electric field model of laterally diffused MOSFET (LDMOS) transistors under the condition of high current injection effect used for reliability simulations. LDMOSs operate under high-voltage and large-current biases, where electric field increases with biases at the gate edge. We present the investigation, formulations, and verifications of our maximum electric field model.
This paper describes redundant successive approximation register (SAR) ADC design methods to improve reliability and conversion speed by digital error correction. Especially we show that redundant SAR ADC using Fibonacci sequence and its property called Golden ratio can be well-balanced design. We also present some simple golden-ratio-weighted DAC topologies for easy realization of the redundant SAR...
This paper describes redundant successive approximation register (SAR) ADC design methods which enable high-reliability and high-speed AD conversion using digital error correction. Especially we propose to apply Fibonacci sequence and its property called Golden ratio to SAR ADC design to optimize redundant search algorithms. We present some interesting properties for well-balanced redundant SAR ADC...
The purpose of this paper is to characterize and model the self-heating effect (SHE) of multifinger n-channel MOSFETs (nMOSFETs). The amount of SHE is small enough not to be analyzed for single-finger bulk CMOS devices. However, SHE should be considered for multifinger nMOSFETs that are mainly used for RF-CMOS applications. The SHE mechanism was analyzed based on a 2-D device simulator. SHE model...
A glitch-free time-to-digital converter (TDC) based on Gray code is presented. This architecture can reduce hardware, power consumption, as well as chip area significantly compared to a flash type TDC, while keeping comparable performance and glitch-free characteristics. Its proof-of-concept prototype was implemented on FPGA, and the measurement and simulation results validate the effectiveness of...
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