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We demonstrate a new post-fabrication trimming technique to fine-tune the phase of integrated Mach-Zehnder Interferometers (MZIs), enabling permanent correction of typical fabrication based phase errors. Preliminary results demonstrate a phase trimming accuracy of 0.146π.
We present our recent work on fibre-chip grating couplers operating around 1310 nm. For the first time, we demonstrated the combination of dual-etch and apodization design approaches which can offer state of the art performance. Initial tests from fabricated structures show a −2.2dB loss.
The design and characterization of a silicon-on-insulator planar concave grating based (de)multiplexer operating at 3.8µm is reported. Low insertion loss (≈1.6dB) and good crosstalk characteristics (≈19dB) are demonstrated.
An SRAM design in a 3D 0.18 m silicon-on-insulator technology is presented. A novel delay-locked loop based access time measurement circuit was designed on-chip for accurately evaluating the 3D SRAM performance. Results show that a 32 improvement in the access time is gained by using 3D technology.
Silicon dioxide has very high optical loss at mid-infrared wavelengths. Here we describe the first shallow-etched grating coupler for a silicon-on-sapphire waveguide at mid-infrared wavelengths, verified with a Er/Pr co-doped ZBLAN fiber laser (2.75 mum wavelength).
Unique hybrid approach employing both model-based layout optimization and process improvement was successfully developed for reducing rapid thermal anneal (RTA) driven intra die variations. It has been applied to multiple bulk and SOI designs. The model developed herein enables fast estimation of broad-band reflectance of a random layout in 65 nm, 45 nm, and 32 nm nodes and guides reflectance leveling...
We compare experimentally the performance of a linearly chirped waveguide grating with a uniform grating for coupling light to a vertical fiber. The measurements show the chirped grating reduces reflection and coupling loss by 2 dB.
We present a 45-nm SOI CMOS technology that features: i) aggressive ground-rule (GR) scaling enabled by 1.2NA/193nm immersion lithography, ii) high-performance FET response enabled by the integration of multiple advanced strain and activation techniques, iii) a functional SRAM with cell size of 0.37mum2, and iv) a porous low-k (k=2.4) dielectric for minimized back-end wiring delay. The list of FET-specific...
We investigate experimentally and theoretically self-phase modulation and group velocity dispersion induced spectral broadening of picosecond pulses in silicon wires. Already for very low peak powers the limit for dense wavelength demultiplexing is reached.
A high performance 65 nm SOI CMOS technology is presented. Dual stress liner (DSL), embedded SiGe, and stress memorization techniques are utilized to enhance transistor speed. Advanced-low-K BEOL for this technology features 10 wiring levels with a novel K=2.75 film in selected levels. This film is a SiCOH-based dielectric optimized for stress to enable integration for enhanced performance. The resulting...
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