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Optical interconnects using polymer waveguides on circuit boards have been demonstrated. Wirebond-free ultradense transceivers provide 160 Gb/s bidirectional throughput with 16 parallel waveguide-connected transmitters and receivers. Initial designs use 985 nm VCSELs. Migration to the industry-standard 850 nm VCSEL wavelength is underway, also providing lower waveguide loss.
We have developed a die-to-wafer integration technology for high yield and throughput for the formation of high bandwidth, high performance, and short-distance interconnections in three-dimensional (3D) stack applications. The results show that multiple 70-mum thick die can be successfully assembled in stacks on top of a wafer using a single bonding step, rather than by repeated sequential bonding...
Three-dimensional (3D) chip integration may provide a path to miniaturization, high bandwidth, low power, high performance and system scaling. Integration options can leverage stacked die and/or silicon packages depending on applications. The enabling technology elements include: (i) through-silicon-vias (TSV) with thinned silicon wafers, (ii) fine pitch wiring, (iii) fine pitch interconnection between...
A parallel optical transceiver module with 24-transmitter plus 24-receiver channels has been designed and fabricated. The transceiver Optochip relies on silicon carrier technology to provide a high level of integration of the electrical and optical components onto a single substrate with high density interconnection. The transceiver Optochip consists of the Si carrier platform with 4 flip-chip attached...
In this paper a three-dimensional (3D) chip stacking technology using fine-pitched interconnects with lead-free solder is described. Different interconnect metallurgies such as Cu/Ni/In, Cu/In and Cu/Sn were considered and the bonding conditions to optimize the bonding parameters were determined. The effect of intermetallic compound (IMC) formation on the mechanical properties of the joins is discussed...
As chip I/O count continues to increase, the C4 bump pitch needs to be further reduced. In this work, a Si-based test carrier was used for characterization of ultra-fine pitch micro C4s. Successful assembly and rework of die with 11,892 micro C4s were demonstrated. The micro C4 contact resistance was measured for various pad geometries. The mechanical shear force was characterized for several variables...
System-on-Chip (SOC) and System-on-Package (SOP) technologies each have advantages depending on application needs. As system architects and designers leverage ever-increasing CMOS technology densities, a range of two- and three-dimensional silicon integration technologies are emerging which will likely support next-generation high-volume electronic applications and may serve high-performance computing...
A silicon-based system-on-package (SOP) is described. Novel capabilities of SOP are expected to enable lower cost, more efficient and higher performance electronic systems. Newly developed technology elements include: electrical silicon through-vias, fine-pitch, high bandwidth wiring, fine pitch solder interconnection, fine pitch known-good-die, and advanced microchannel cooling. Applications may...
The design, fabrication, assembly and characterization of a novel silicon carrier package used for enabling a Tb/s parallel optical transceiver is reported. Electrical through-vias, high speed wiring and a through cavity for housing optoelectronic (OE) devices are critical features of the silicon carrier that allow high density integration of optical and electrical components on a single substrate,...
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