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Electrical properties of silicon-dot-based single-electron memory devices were investigated using numerical simulation. For an accurate calculation of tridimensional electron wave functions in the dots and in the dot-isolation surrounding the nextnano++ simulator was employed. Tunneling rates between the dot and other electrodes were calculated using a post-processing of the electron-state-specific...
n-channel 4H-SiC MOSFETs were manufactured and characterized electrically at room temperature by current-voltage and Hall-effect measurements as well as by numerical simulations. To describe the observed electrical characteristics of the SiC MOSFETs, Near-Interface Trap (NIT) and charge carrier mobility degradation models were included in the simulation, performed with Sentaurus Device of Synopsys...
A simulation study of lithography induced layout variations in 6-T SRAM cells is presented. Lithography simulations of a complete 6-T SRAM cell layout, including active n+/p+ regions layer and poly-gate layer were performed. The smallest feature size was assumed to be 45 nm. 76 positions of the projector focus were simulated for each layer in total. TCAD simulations of 32nm single gate FD SOI MOSFETs...
Source and relevance of process variations are briefly discussed. A combination of own lithography and commercial TCAD simulation software is applied to assess the impact of some of the most relevant variations occurring in lithography on the electrical properties of three kinds of CMOS devices with 32 nm physical gate length.
The simulation of process options for advanced CMOS devices is discussed in this work. Advanced rapid thermal annealing schemes are applied to fully depleted silicon on insulator MOSFETs with a physical gate length of 22 nm. Process induced mechanical stress is simulated for PMOS transistors to improve the Ion-Ioff relation. A modification of the linear piezo model is presented to simulate the hole...
In this paper, a TCAD-based simulation study on lithography process-induced gate length variations has been performed. This study aims at evaluating fully depleted silicon on insulator (FD SOI) MOSFETs for next generation CMOS devices. Critical dimensions (CDs) have been obtained using rigorous lithography simulations. The impact of the resulting gate length variations on the electrical behavior of...
In this work, the influences of advanced annealing schemes, spike and flash annealing and combinations of them, on the electrical behavior of modern FD SOI MOSFETs have been investigated by numerical simulations. Process simulations have been performed for comparing the two-dimensional diffusion behavior of the dopants under the different annealing schemes. Device simulations have been performed for...
Problems of pre-silicon compact modeling of nano-scaled silicon-on-insulator MOSFETs are addressed using the extraction of SPICE model parameters directly from numerical TCAD simulations. Although there are difficulties in the parameter extraction for the standard SPICE compact models we show by a direct comparison with the results of the numerical mixed-mode TCAD simulations that with some trade-offs...
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