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Set-valued data is comprised of records that are sets of items, such as goods purchased by each individual. Methods of publishing and widely utilizing set-valued data while protecting personal information have been extensively studied in the field of privacy-preserving data publishing. Until now, basic models such as k-anonymity or km-anonymity could not cope with attribute inference by an adversary...
In this study, it is found that the temperature measurement using body diode of SiC-MOSFET is greatly affected by the bias voltage between gate and source, unlike using body diode of Si-MOSFET. We introduce a method that it is possible to measure the junction temperature correctly by applying a suitable negative bias between G-S. Hence, the heat resistance evaluation method for the SiC power module...
In this paper, we demonstrate a high heat resistant bonding method by Cu/Sn transient liquid phase sintering (TLPS) method can be applied to die-attachment of silicon carbide (SiC)-MOSFET in high temperature operation power module. The die-attachment is made of nano-composite Cu/Sn TLPS paste. The die shear strength was 40 MPa for 3 × 3 mm2 SiC chip after 1,000 cycles of thermal cycle testing between...
We have developed a recommendation system of companies for new graduates. In this paper, we defined high/low-browsed companies and constructed the recruitment navigation system of the low-browsed companies suitable for each student from the browsing data. Different from traditional recommendations, we need to deal with the problems that the entry (application) period is limited. The methods applicable...
Thermal resistance evaluation of silicon carbide (SiC) power module for high-temperature operation has been performed in order to define the precise thermal resistance in real package structure. Transient thermal analysis method using SiC-Schottky barrier diode (SBD) is applied to measure the thermal structure function in wide temperature range from 50°C to 250°C. The module structure consists of...
The active-metal-brazed copper (AMC) on Si3N4 ceramic substrate was used to fabricate the all-silicon carbide (SiC) high-temperature power modules. Its reliability was evaluated under the conditions of high-temperature storage (HTS) at 250 °C and thermal cycling test (TCT) from −40 °C to 250 °C. During HTS, the AMC substrate was stable without deformation of the Cu layer. The shear strength of the...
In three-dimensional integrated circuits (3DICs), aggressive wafer-thinning can lead to large thermal gradients. It is crucial to understand the interaction between process parameters, such as wafer thickness, and the temperature profile in order to design high-performance 3DICs. In this paper we examine how the temperature profile of a single TSV bus driver/receiver is impacted by die thinning. Die...
3D LSI chip stacking technology have been developed using cone shape Au micro bumps fabricated by nanoparticle deposition method. The cone shape bumps with less than 10 um diameter are suitable for a thermocompression bump joint process with low temperature and low load force. High yield micro bump joints can be obtained. In this study, the property evaluation of the cone shape bumps, and the cone...
In three-dimensional integrated circuits (3DICs), aggressive wafer-thinning can lead to large spikes in individual device temperatures. These “hotspots” must be carefully analyzed at design time to ensure that the device temperatures will not cause the circuit to malfunction, and to assess the device temperature's impact on the longevity of the circuit. In this paper we present a tool flow for capturing...
3D integrated circuits (3DICs) stack wafers vertically, allowing for heterogeneous integration with shortened wirelengths between multiple circuits. In memory-on-Iogic systems there is a significant concern that high-power sections of the processor will create large thermal gradients that cause logical failures in the stacked memory. In this paper we investigate the use of a microchannel-based interposer...
In this work, SiC power module with sandwich structure is fabricated for high-speed switching operation at high temperature. A module structure of SiC power devices are sandwiched between two silicon nitride-active metal brazed copper circuit boards. To make a precise position and height control of the chip bonding, the top side (gate/source or anode pad side) of SiC power devices are flip-chip bonded...
The high-speed signal transmission characteristics of high density flip-chip interconnect with micro Au bumps were investigated. A test element group device and substrate was designed and fabricated to measure the properties of the high density interconnect structure. The test chip and substrate had Cu wires patterned to create a controlled impedance coplanar waveguide (CPW) transmission line in order...
We propose a new truncation framework for online supervised learning. Learning a compact predictive model in an online setting has recently attracted a great deal of attention. The combination of online learning with sparsity-inducing regularization enables faster learning with a smaller memory space than a conventional learning framework. However, a simple combination of these triggers the truncation...
We have developed a fabrication technology of fine-pitch cone shape Au bump array using nanoparticle deposition method for 3D LSI chip stacking. 1024-bit wide bus chip-to-chip interconnection circuit called Cool Interconnect has been also developed using fine-pitch bump joint array technology and precise flip chip bonding technology. Such a wide bus chip-to-chip interconnection is suitable instead...
In this study, the high-speed signal transmission characteristics of high density flip-chip interconnect incorporating micro Au bumps were investigated. A TEG (test element group) device and substrate was designed and fabricated to measure the properties of the high density interconnect structure. The test chip and substrate had Cu wires patterned to create a controlled impedance CPW (coplanar waveguide)...
A high temperature resistant joint technology for bonding SiC power devices is developed using a transient liquid phase sintering (TLPS) process with a paste containing Cu and Sn powders with the size less than 15µm. The SiC devices are bonded to the Si3N4/Cu/Ni(P) substrate with the TLPS process at 260°C in a N2 atmosphere for 20 minutes. The microstructure of the bond is mainly composed of Cu6Sn...
3-D Multi-Chip stacking is a promising technology to overcome the “memory wall”, “power wall”, “ILP wall”, and “utilization wall”. However, a chip to be stacked should be low-power enough to avoid heat issue. On the other hand, such system can benefit from its scalability, flexibility, short time-to-market, especially wide and short latency chip interconnect drives changes on microprocessor architecture...
In this work, three CMOS ring oscillator chips designed for hot spot generation in the LSI device are employed on a Si substrate with the thickness of 525 μm and a thin Si substrate with the thickness of 100 μm. Since a hot spot is observed on the 100 μm thick substrate, a high thermal conductivity film of 10 μm-thick is integrated on the reverse side of the thin substrate as a heat spreader. The...
Many clustering methods have been proposed for analyzing the relations inside networks with complex structures. Some of them can detect a mixture of assortative and disassortative structures in networks. All these methods are based on the fact that the entire network is observable. However, in the real world, the entities in networks, for example a social network, may be private, and thus, cannot...
3D multi-chip stacking is a promising technology poised to help combat the “memory wall” and the “power wall” in future multi-core processors. However, as technology scales and the chip sizes increase due to the number of transistors, interconnects have become a major performance bottleneck and a major source of power consumption for microprocessors. In this article, we introduce a TSV-based ultra-wide...
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