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Aim: Adipogenous tissue derived stem cells (ADSC) are available in abundance in the human body and can differentiate in the presence of lineage-specific induction factors in myogenic, adipogenic, chondrogenic and osteogenic cells. The aim of this study was to evaluate the impact of osteogenic induced ADSC’s (O-ADSC) on revascularization and cellular repopulization of avital cortical bone...
Feature-scale simulation of sputter etching has been coupled to equipment parameters by means of transferring angular distributions of ions as provided by equipment simulation to our simulation code. Etching is modeled by performing ion flux integration for all node positions on a discretized 3D surface, taking into account shadowing by the geometry, the angular distribution of ions, and the sputtering...
Rutherford Backscattering Spectroscopy was used to analyze and quantify the out-diffusion of Cs and Rb from silicon during solid-phase epitaxial regrowth under N2 atmosphere. Out-diffused amounts of about 60% Rb and 30% Cs were determined. The transient out-diffusion behavior of the alkali atoms in ultra-high vacuum was monitored during recrystallization by secondary neutral mass spectroscopy. The...
Polypropylene (PP) films for thin film capacitors were implanted with N, Ar, and Ne, respectively, in order to reduce the water vapor permeability. It is shown that the reduction of the water vapor permeability strongly depends on implantation dose and energy. For doses below 1015 cm−2, the water vapor permeability was not affected, while doses above 1015 cm−2 lead to a significant reduction. For...
This paper presents improvements in resizing single crystalline Si wafers by using the dicing technology “Thermal Laser Separation” (TLS). Results of this work support the general need to resize wafers to smaller diameters and will play an important role during the transition to larger wafer diameters as currently projected in the ITRS for 450 mm: Wafers of new sizes have to be easily adapted to fit,...
In this work, we present a monolithic RC-snubber for power electronic applications that outperforms state of the art RC-snubbers in terms of characteristic electrical parameters. The principle device structure as well as the process technology is presented. The outstanding properties of the device are a high capacitance per area (1.5 nF/mm2), a low temperature coefficient of the capacitance value...
ZnO-based thin film transistors (ZnO-TFTs) were fabricated by sputtering of ZnO on 200 nm SiO2 on p+-Si substrates. Forming gas annealing (FGA) was carried out directly after deposition at 400°C, 450°C, and 500°C for 1h. TFTs annealed at 400°C exhibited a high threshold voltage (VTh) of 11 V while those annealed at 500°C showed a low VTh of -3 V. Saturation mobility (μsat) increased slightly with...
The simulation of process options for advanced CMOS devices is discussed in this work. Advanced rapid thermal annealing schemes are applied to fully depleted silicon on insulator MOSFETs with a physical gate length of 22 nm. Process induced mechanical stress is simulated for PMOS transistors to improve the Ion-Ioff relation. A modification of the linear piezo model is presented to simulate the hole...
This paper presents a packaging technology for passive devices and characterization results of a demonstrator. Due to high demands on weight, cost and size this demonstrator was chosen to show the potentials of highly filled polymers for packaging solutions in power electronics especially for automotive and aerospace applications. As a demonstrator a choke for a high power multiphase 100 kW DC/DC...
In this paper, a TCAD-based simulation study on lithography process-induced gate length variations has been performed. This study aims at evaluating fully depleted silicon on insulator (FD SOI) MOSFETs for next generation CMOS devices. Critical dimensions (CDs) have been obtained using rigorous lithography simulations. The impact of the resulting gate length variations on the electrical behavior of...
In this work, new results on an active fuse which is a novel power device to prevent serious hazards in power electronics in the case of a malfunction are presented. The focus of this work is on the characterization of the ldquocutout-bridgerdquo in terms of functionality and reliability. Different cutout-bridge geometries and the dc-arc behavior during fuse release is analyzed and by utilizing an...
In this work, the influences of advanced annealing schemes, spike and flash annealing and combinations of them, on the electrical behavior of modern FD SOI MOSFETs have been investigated by numerical simulations. Process simulations have been performed for comparing the two-dimensional diffusion behavior of the dopants under the different annealing schemes. Device simulations have been performed for...
A method for decreasing the parasitic source and drain contact resistances in decanano-scaled CMOS devices is presented in this work. The improvement of the electrical performance of the CMOS devices has been achieved by increasing the active contact area, without increasing the complete layout area consumption of the device, for lowering the parasitic source/drain contact resistances. Numerical simulations...
Problems of pre-silicon compact modeling of nano-scaled silicon-on-insulator MOSFETs are addressed using the extraction of SPICE model parameters directly from numerical TCAD simulations. Although there are difficulties in the parameter extraction for the standard SPICE compact models we show by a direct comparison with the results of the numerical mixed-mode TCAD simulations that with some trade-offs...
The continuous dimensional reduction for micro-and nano electronics is driving the technology for yield relevant defect detection. Defects originating in the crystal are always present in silicon wafers. Due to miniaturization, the size of these defects becomes comparable to the feature sizes of future technology generations. Therefore, they are identified as a future yield limiting mechanism. This...
In this work, we introduce a high voltage 3D-capacitor as a novel passive power device for a 400 V application. This device is realized in silicon technology which allows process reproducibility, high accuracy in capacitance values, and high quality of the dielectric layers (i.e., endurance at high electric field strengths). It can be manufactured discrete or as part of a monolithic integrated circuit...
The pile up of As at the SiO2/Si interface was investigated by grazing incidence X-ray fluorescence spectroscopy in combination with removal of silicon layers by etching with thicknesses on the order of a nanometer. In order to determine the thickness of the silicon layers removed at the interface, atomic force microscope measurements were performed at trench structures. With this method, it is possible...
This paper describes the objectives and results of a joint European project named flying wafer. The goal of the project was to provide a methodology for interlinking European R&D centers in micro- and nanotechnologies to a distributed 300 mm CMOS R&D line. The project was carried out as a feasibility study. Therefore, the results provide a model and concept which has the potential of guaranteeing...
In this work, we propose an active fuse which is a novel power device to prevent serious hazards in power electronics in the case of a fault. Using this active fuse, power devices or parts of power electronic circuits which are in an undefined, uncontrollable condition can be disconnected reliable and irreversible from the power supply. Critical safety consequences of faults like overheating or fire...
In this work, we propose an insulated gate bipolar transistor (IGBT) with a novel lateral triple trench gate architecture, which shows a four times higher forward conduction current compared to devices with a lateral gate or single trench gate structure. For the proof of concept, we realized single trench gate IGBTs using the reduced surface field (RESURF) principle [J.A. Appels, H.M.J. Vaes, A.W...
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