This paper describes the objectives and results of a joint European project named flying wafer. The goal of the project was to provide a methodology for interlinking European R&D centers in micro- and nanotechnologies to a distributed 300 mm CMOS R&D line. The project was carried out as a feasibility study. Therefore, the results provide a model and concept which has the potential of guaranteeing a safe and fast exchange of wafers and data between European R&D nodes to allow multi-site processing. An implementation phase is planed in a second step.