The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The paper addresses a top-down design flow of depletion-load digital inverter formed by monolithically integrated depletion-mode and enhancement-mode high electron mobility transistors (HEMTs) on common InAlN/GaN heterostructure grown on sapphire substrate. We describe the inverter design at transistor level using HSPICE models developed earlier. The inverter layout representation, which also defines...
This paper addresses a design and performance evaluation of a non-clocked comparator circuit intended to work in a wide temperature range with very low value of the power supply voltage. Due to low voltage swing, the input voltage range is set to be rail-to-rail. The target fabrication process is a standard twin-well 130 nm CMOS technology, with appropriate parameters required to meet circuit specifications...
The article addresses a design procedure of low-power variable gain amplifier employing so-called bulk-driven transistors in 130 nm CMOS technology, working with the power supply voltage of only 600 mV. Mentioned approach represents rather unconventional and still quite uncharted design technique. Therefore, the research potential is tremendous. The paper describes the proposed amplifier along with...
Different low-voltage and low-power techniques, which meets modern integrated circuit design requirements, appears as the key towards achievement of enhanced performance of designed circuits. For deep sub-micron technologies, choosing a suitable transistor model becomes very important. Conventional MOS transistor models, such as BSIM or PSP, are developed for conventional gate-driven applications...
The paper addresses the design of a bulk-driven variable gain amplifier (VGA) in 130 nm general purpose CMOS technology. The VGA is intended to be employed within a low-power automatic gain control (AGC) block, which requires an examination of possible gain setting approaches. The mentioned investigation as well as the evaluation and comparison of the obtained results are presented. The amplifier...
The paper deals with design and analysis of a variable-gain amplifier (VGA) working with a very low supply voltage, which is targeted for low-power applications. The proposed amplifier was designed using the bulk-driven approach, which is suitable for ultra-low voltage circuits. Since the power supply voltage is less than 0.6 V, there is no risk of latchup that is usually the main drawback of bulk-driven...
In this paper, a variable gain amplifier designed in 130 nm CMOS technology is presented. The proposed amplifier is based on the bulk-driven approach, which brings a possibility to operate with low supply voltage (i.e. 0.6 V). Since the supply voltage of only 0.6 V is used for the amplifier to operate, there is no latchup risk that usually represents the main drawback of the bulk-diven approach. As...
An alternative method of fault simulation is presented in this paper. The proposed method is based on impedance calculations in the circuit under test. Calculation time and other properties of the method are addressed and evaluated. Possible application and results evaluation are demonstrated on an experimental circuit. This method could improve the test development time and quality.
The article addresses design and development of logic gates and circuits fabricated on InAlN/GaN/Sapphire heterostructure employing an in-house technology process. Designed circuits are intended to execute the fundamental Boolean logic operations as well as the memory function covered by RS latch circuitry. The paper describes the complete design flow of logic cells, investigation and statistical...
This paper presents the frontend part of the readout interface for a capacitive MEMS microphone designed and fabricated in 0.35 μm CMOS technology. The developed readout interface will be used in a noise dosimeter applicable in very noisy and harsh environment. The prototype chips were measured and the main parameters evaluated. The achieved results demonstrate low harmonic distortion, low noise and...
The article addresses a design methodology of globally asynchronous locally synchronous (GALS) digital systems from the designer's point of view. It discusses the nature of this special type of electronic circuits, its advantages as well as drawbacks as comparison to standard synchronous and asynchronous systems. Furthermore, it describes the top-down design flow for various implementation approaches...
This paper addresses a development of self-heating electro-thermal model of a system-in-package (SiP) occupying several silicon dies within one IC package. Proposed model maintains very high accuracy of modeled parameters in the wide range of dynamic temperature fluctuations, which brings the thermal simulations of state-of-the-art ICs much closer to the real scenario. Presented work also introduces...
Path delay faults are tested via selected critical paths in a tested digital circuit. The critical paths can be specified e.g. by static timing analysis (STA), dynamic timing analysis (DTA) and others. Many parameters such as multiple input switching, power supply noise, type of propagated signal edge (rising, falling) and others affecting the signal delay propagation and thus they can increase path...
Presented work introduces automated interaction of SDevice and HSPICE for fast 3-D electrothermal simulation. The proposed methodology maintains a very high accuracy of the modelled parameters in a wide range of dynamic temperature fluctuations, which brings the thermal simulations much closer to the real state. The designed electrothermal simulation is developed for Synopsys TCAD Sentaurus environment...
This article describes the design procedure towards a robust digital inverter that is intended to be fabricated on InAlN/GaN material heterostructure. Heterojunction field effect transistors (HFETs), regardless the material used, exhibit exceptional power delivery at high frequencies and also outstanding capability to withstand the operation in a very harsh environment. These properties make HFET...
This article addresses an overview of design procedure of digital inverters employing heterostructure field-effect transistors (HFETs) based on InAlN/GaN material structure. InAlN/GaN HFETs are well-known for their high frequency, high power properties and their ability to withstand very harsh environmental effects. These attributes predestine their use in a wide range of applications. However, the...
This paper addresses a behavioral model development of a high frequency voltage regulator (HFVR) unit with self-heating effects included. Recent power management circuits can dissipate a significant portion of heat that might affect the overall performance of the system. During the design of the systems, based on discrete components, engineers almost exclusively rely on static ambient temperature...
This paper addresses a novel methodology of detecting the completion of computation process of the combinatorial block in asynchronous systems. Logic gates fabricated in CMOS technology draw electrical current in several orders of magnitude higher during the signal transitions than in the idle state. This fact can be used to separate the idle state and the computing activity. The paper presents the...
An on-chip current monitor designed in 90 nm CMOS technology is addressed. Proposed circuit exhibits wide temperature operating range as well as the stability over the process corners. First part of the article describes the theoretical background of employed design technique. Second part addresses proposed sensor topology and achieved parameters for a specific design. Finally, conclusion as well...
Current Sensing Completion Detection (CSCD) method in asynchronous circuits is addressed. Current Sensing represents a simple but effective and reliable approach to detect completion of computation in asynchronous (self-timed) systems. However, in recent deep sub-micron technologies, several challenges, such as significant influence of process variations, leakage current power dissipation with circuit...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.