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This paper presents the design of a high-voltage (HV) rail-to-rail error amplifier. This circuit controls the output signal of a low drop-out voltage regulator (LDO) according to the reference voltages and based on stacked standard transistors. The circuit is designed using 65 nm CMOS process technology with a nominal voltage of 2.5 V and is optimized for arbitrary values of supply voltage up to 5...
This paper presents a high-voltage (HV) driver for switching a buck converter. The circuit is based on 3-stacked CMOS using gate control circuits to drive maximum current which indicates minimized on-resistance of the HV-driver thus achieving faster switching. The circuit is designed and fabricated using 65 nm CMOS TSMC process technology with a nominal voltage of 2.5 V and with a supply voltage of...
This paper presents the design of two high-voltage level shifters suitable for a wide range of supply voltages. In view of certain drawbacks identified during the design, implementation, simulation and measurement of a 3-stacked CMOS driver using capacitive feedback level shifters, improved high-voltage level shifters are designed. These circuits are compared with each other in terms of their circuit...
This paper presents the design of a high-voltage driver with an adapted level shifter for switching converters. The proposed HV-driver and level shifter are based on stacked standard CMOS, therefore the design is technology independent. The circuit is designed in 65-nm TSMC technology with a nominal voltage of 2.5 V and optimized for arbitrary supply voltages from 2.6 V to 6.0 V. This range is extended...
This paper presents the design of a high-voltage driver based on stacked standard low-voltage CMOS with an adapted level shifter. Both circuits are designed in 65-nm TSMC technology with a nominal voltage of 2.5 V without any passive elements. The control voltages to regulate the stacked transistors of the HV-driver are achieved by proposing cascode self-biasing method, therefore no reference voltages...
This paper presents the design of a high-voltage differential amplifier using six different pre-input stage circuits to reduce high-voltage input levels to low-voltage signals. The proposed circuits are designed using 65 nm CMOS process technology with a nominal voltage of 2.5 V and a supply voltage of 5 V. The designs are based on stacked low-voltage standard CMOS transistors. The different pre-input...
A regulation scheme to linearize the tuning curve of CMOS ring oscillators is proposed in this paper. The scheme uses the current consumption of the CMOS ring elements, which is proportional to the output frequency to the first order. The design of the feedback loop is presented on system level in conjunction with performance enhancements made on the implementation level. A weakly non-linear ring...
We present in this paper the design of an integrated asynchronous buck converter with improved power conversion efficiency. A threshold compensated freewheeling diode is introduced to the converter to minimize both the diode forward voltage drop as well as the reverse leakage current. In order to enable monolithic high voltage switching, serially stacked MOS transistors are utilized. The buck converter...
This paper presents a new concept for reducing on-resistance of high-voltage drivers based on stacked MOSFETs for various supply voltages. A theory to calculate gate voltages of an N-stacked CMOS driver to drive the maximum drain current at a minimum on-resistance is introduced. According to the calculated gate voltages, a circuit design methodology is described to generate them. The principle is...
This paper presents a new technique for reducing on-resistance of high-voltage drivers, which are based on N-stacked standard CMOS. A theory to calculate gate voltages of HV-driver transistors to drive the maximum drain current for minimum on-resistance is introduced. According to the calculated gate voltages, a circuit design methodology for generating them is described. This concept is technology...
This paper presents a low drop-out voltage regulator (LDO) suitable for input voltages twice the nominal operating voltage of the CMOS technology. High GBW and good DC accuracy in line and load regulation is achieved by using 3-stage error amplifiers. Two feedback loops are used to improve stability. High voltage compatibility is established by stacking two pass transistors. The first pass transistor...
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