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Three-Dimensional (3D) integration of group III–V compound semiconductor devices on silicon (III–V/Si) is important for next-generation microsystems such as Si photonics or ultra-high-frequency electronics. We proposed a new “Chip-on-Wafer Direct Transfer Bonding” (CoW DTB) technology for III–V/Si applications. The technology concept was demonstrated using newly developed equipment and bond evaluation...
In order to realize optical interconnection for high-speed low-latency direct-attached storage in a data center, we developed double-threshold automatic gain control (AGC) that enables reliable optical out-of-band (OOB) transmission in de facto standard storage interfaces such as Serial ATA (SATA) and Serial Attached SCSI (SAS). OOB is quasiternary signaling composed of differential burst signals...
Three-Dimensional (3D) integration of group III-V compound semiconductor material on Si wafer (III-V/Si) is important for next-generation microsystems such as Si photonics or ultra-high-frequency electronics. A technique for direct bonding of III-V chips on a large-diameter Si wafer is an attractive approach for manufacturing these structures, but there is a difficulty in that ultra-clean particle-free...
In order to realize reliable OOB (Out-of-Band) transmission which is a major problem in optically connected SATA (Serial ATA) or SAS (Serial Attached SCSI), 12.5 Gb/s driver and receiver ICs with a newly-developed double threshold AGC were fabricated by TSMC 90 nm CMOS process. The double threshold AGC realized the rejection of small noise in a transmission line in an idle condition and the suppression...
We demonstrated high-speed, stable and unidirectional microring III-V laser diodes with in-cavity feedback silicon waveguide, and the integration with III-V photodetector on a silicon-on-insulator platform to achieve on-chip data transmission with a data rate of 12.5 Gb/s.
We have developed a new system-in-package (SiP) called a “System in Wafer-Level Package” (SiWLP). It is fabricated using “RDL-first” technology for fan-out wafer-level-packages (FO-WLPs) and provides high chip-I/O density, design flexibility, and package miniaturization. We developed this SiWLP by using multilayer RDLs and evaluated its unique packaging processes. We achieved high-throughput fabrication...
We have developed a new Fan-Out Wafer-Level Packaging (FO-WLP) technology with flexible design capabilities for multilayer fan-out redistribution layers (RDLs) connected to the fine-pitch I/O pads of chips. The prototype of a 2.0 mm × 2.0 mm FO-WLP with 25-pin land grid array (LGA) including a 1.6 mm × 1.6 mm microcontroller chip was fabricated and evaluated. Board-level reliability was also confirmed...
A general-purpose 3D-LSI platform technology for a high-capacity stacked memory integrated on a logic device was developed for high-performance, power-efficient, and scalable computing. SMAFTI technology [1-5], featuring an ultra-thin organic interposer with high-density feedthrough conductive vias, was introduced for interconnecting the 3D stacked memory and the logic device. A DRAM-compatible manufacturing...
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