The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Transactional memories with support for real-time and reliability requirements are a research challenge for the deployment in safety-critical embedded systems. In addition, at present there are no transactional-memory architectures considering hierarchical systems of networked multi-core chips with both on-chip and off-chip networks. The presented work offers a predictable transactional memory solution...
We propose the integration of a network-on-chip-based MPSoC in mixed-criticality systems, i.e. systems running applications with different criticality levels in terms of completing their execution within predefined time limits. An MPSoC contains tiles that can be either CPUs or memories, and we connect them with an instance of a customizable point-to-point interconnect from STMicroelectronics called...
The pervasiveness of multi-core platforms and the trend towards mixed-criticality applications are major technology drivers in the area of embedded systems. Although transactional memories offer the potential to radically simplify the development of these systems, fault isolation and temporal predictability are open research challenges. This paper introduces a priority-based hardware transactional...
Transactional memories can radically simplify the programming of mixed-criticality systems by offering atomicity, consistency and isolation guarantees between subsystems of different criticality. A major objective in mixed-criticality systems is a modular safety case where each subsystem is certified to the respective safety assurance level. The prerequisite for this modular certification is the prevention...
The extension of time-triggered message-based on-chip architectures towards an AUTOSAR MPSoC platform helps to achieve the AUTOSAR goals, in particular with respect to fault isolation and temporal predictability. Simulation environments enable early analysis and performance tests of the software for MPSoC platforms. However, there is no simulation environment that combines on-chip network communication...
Multi-core processors promise improved performance and a higher physical integration by combining functions of different criticality levels in one platform. Networked multi-core chips are required to achieve a system reliability beyond the reliability of a single chip and to satisfy resource requirements exceeding the capacity of a single chip. As a consequence, hierarchical platforms emerge in which...
The simulation of networked multi-core chips is a significant research problem in large embedded applications. Although multi-core processors in embedded systems offer increased computational resources and performance, many applications still require distributed systems with multiple of these processors to satisfy resource requirements and provide fault-tolerance at system level. This paper introduces...
Multi-Processor Systems-on-a-Chip (MPSoC) based on time-triggered on-chip networks facilitate fault isolation, temporal predictability and mixed-criticality integration. In mixed-criticality systems, a shared memory can be realized on top of time-triggered message passing to effectively support heterogeneous applications with different interaction paradigms. This paper presents a simulation environment...
Mixed-criticality systems combine applications at different levels of criticality on the same platform. Today, mixed-criticality integration is addressed individually at different integration levels such as the operating system, the chip-level and the cluster-level. Since many mixed-criticality systems span all of these integration levels, a system perspective of mixed-criticality applications is...
Today's Ambient Assisted Living (AAL) architectures do not support the real-time and reliability requirements of medical monitoring and closed-loop control applications. Fault-tolerant embedded system architectures, on the other hand, do not address the openness required for the dynamic integration of AAL components. This paper present an AAL architecture based on Time-Triggered Ethernet with support...
In this brief, an efficient implementation of an 8-bit Manchester carry chain (MCC) adder in multioutput domino CMOS logic is proposed. The carries of this adder are computed in parallel by two independent 4-bit carry chains. Due to its limited carry chain length, the use of the proposed 8-bit adder module for the implementation of wider adders leads to significant operating speed improvement compared...
Dynamic circuit design techniques can provide high speed operation at lower silicon area requirements, compared to full static CMOS designs. In this paper, we present a memoryless pipeline dynamic design technique with a pre-evaluation phase hidden inside the precharge phase. The combinational logic is implemented with dynamic circuits that offer the desirable high speed operation while the memory...
A desirable characteristic of VLSI circuits is high speed operation. The use of dynamic circuit design techniques can provide high speed operation at lower silicon area requirements, compared to full static CMOS designs. Another common design technique in order to achieve high operating speed is the use of pipeline schemes. However, the higher the required operating frequency, the higher the number...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.