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This paper describes FieldRC, a fast and accurate, Design-for-Manufacturing (DFM) aware, Monte-Carlo (MC) based parasitic extractor for computing interconnect capacitance (C) and resistance (R) in VLSI designs. A novel rejection sampling technique rapidly solves capacitance in multiple dielectric environments using a small memory footprint (∼2GB) even for large designs to 200K nets. For the first...
An electrical methodology to extract the complete set of interconnect process parameters is developed. A new structure comprising a combination of integrated meander resistor and a comb-capacitor sandwiched between bottom and top plates is proposed. Its electrical characterization provides all the necessary measurement data required for reliable and robust extraction of interconnect parameters, namely,...
The inductance effects become significant for sub-100nm process designs due to increasing interconnect lengths, lower interconnect resistance values and fast signal transition times. The accurate modeling of inductance behavior is thus essential for high speed VLSI designs. Recently X architecture has been introduced to reduce overall IC interconnect length by using diagonal wirings pervasively, resulting...
In this paper we report a physically based thin gate oxide MOSEET model for ULSI circuit simulations. It is shown that to accurately model current and capacitances in these devices down to 0.1??m channel length, one must use effective gate oxide thickness that is larger than the physical thickness in the classical MOSFET circuit models. The increase in the effective Tox from its physical value depends...
The impact of reduced polysilicon doping concentration Np on circuit performance is analyzed using a new polysilicon depletion model. SPICE simulations of inverter chains with different loadings predict that higher circuit delays are expected as Np is reduced. The performance degradation gets compounded when the gate oxide thickness tox is reduced, and/or substrate concentration Nb is increased. For...
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