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CLEAR (Cross-Layer Exploration for Architecting Resilience) is a first of its kind framework which overcomes a major challenge in the design of digital systems that are resilient to hardware errors: achieve desired resilience targets at low cost (energy, power, execution time, area) by combining resilience techniques across various layers of the system stack (circuit, logic, architecture, software,...
We present a first of its kind framework which overcomes a major challenge in the design of digital systems that are resilient to reliability failures: achieve desired resilience targets at minimal costs (energy, power, execution time, area) by combining resilience techniques across various layers of the system stack (circuit, logic, architecture, software, algorithm). This is also referred to as...
Analyzing design vulnerability for soft errors has become a challenging process in large systems with a large number of memory elements. Error injection in a complex system with a sufficiently large sample of error candidates for reasonable accuracy takes a large amount of time. In this paper we describe RAVEN, a statistical method to estimate the outcomes of a system in the presence of soft errors...
Statistical fault injection is widely used for analyzing hardware in the presence of soft errors. Although this method can give accurate results for averaged erroneous outcomes with a fairly small sample size, it will not be accurate for vulnerability analysis of each sequential element in the design with small sample sizes. This paper describes a novel and highly efficient technique which is suitable...
Evaluating the fault coverage of manufacturing tests has become a time-consuming process due to today's large and complex digital designs. The computation cost is even more pronounced in software-based self test, on-line test, and logic BIST schemes, which require fault simulation of sequential circuits. In this paper, we build a regression model for estimating stuck-at fault coverage. This model...
Evaluating the coverage of tests for large circuits is computationally very intensive, particularly for logic BIST, software-based self test and on-line test schemes. This has led to research into techniques for rapidly evaluating the coverage of proposed test. We introduce a new metric which is highly correlated with fault coverage measured by gate-level simulators. Based on this metric, we estimate...
Soft errors, caused by radiation, have become a major challenge in today's computer systems and networking equipment, making it imperative that systems be designed to be resilient to errors. Error injection is a powerful approach to evaluate system resilience, and current practice is to inject errors in architectural registers of processors, program variables of applications, or storage elements in...
Choosing the correct error injection technique is of primary importance in simulation-based design and evaluation of robust systems that are resilient to soft errors. Many low-level (e.g., flip-flop-level) error injection techniques are generally used for small systems due to long execution times and significant memory requirements. High-level error injections at the architecture or memory levels...
FALCON (FAst fauLt COverage estimatioN) is a scalable method for fault grading which uses local fault simulations to estimate the fault coverage of a large system. The generality of this method makes it applicable for any modular design. Our analysis shows that the run time of our algorithm is related to the number of gates and the number of IOs in a module, while fault simulation run time is related...
This paper proposes a novel and efficient method for RT level online testing. Our method makes every RT-level resource online-testable, and guarantees high single stuck-at fault detection (i.e., high reliability) with low area/latency overhead. This method uses available resources in their dead intervals (the intervals during which a resource is not being used) to test active resources. The area and/or...
This paper presents a novel fault simulation environment in VHDL. By writing a library of special fault simulation models, a traditional model is transformed into a new model that performs fault simulation using a VHDL simulation engine. Pre- and post-synthesis VHDL models are used for an effective implementation, better performance and to minimize the overhead associated with VHDL simulation. Models...
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