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Chip lifetime degradation due to oxide breakdown is a major concern for today's designers. We review existing methods to solve the gate oxide reliability issues and also introduce an in situ degradation monitoring technique. This technique allows early detection of oxide degradation and makes a system aware of its reliability. When used in conjunction with reliability management schemes, it minimizes...
We present an in situ approach to detect the initial onset of oxide breakdown in large-scale circuits for wearout detection and management. The detection is based on a change in the resistive behavior of the oxide from non-linear to linear. Two 65 nm test-chips show robustness under temperature variation and capture of the onset of failure after just 0.5% delay increase in a FIR filter.
Oxide breakdown has become an increasingly pressing reliability issue in modern VLSI design with ultra-thin oxides. The conventional guard-band methodology assumes uniformly thin oxide thickness and results in overly pessimistic reliability estimation that severely degrades the system performance. In this study we present the use of limited post-fabrication measurements of oxide thicknesses from on-chip...
We review adaptive design techniques with particular emphasis on error-tolerant techniques. We compare and contrast traditional adaptive approaches with error-tolerant techniques and analyze the margins eliminated by each of them. We discuss the applications of the latter to on-chip communication and signal-processing. Finally, we focus on a specific example of an error-tolerant technique for general-purpose...
Due to reduction in device feature size and supply voltage, the sensitivity of digital systems to transient faults is increasing dramatically. As technology scales further, the increase in transistor integration capacity also leads to the increase in process and environmental variations. Despite these difficulties, it is expected that systems remain reliable while delivering the required performance...
Continued technology scaling exacerbates the incidence of degradation and failure in integrated circuits due to mechanisms such as oxide breakdown, negative bias temperature instability and electromigration. This work analyzes the impact of different factors on lifetime distributions for the oxide breakdown effect using a novel monte carlo approach based upon the percolation model and BSIM4. Results...
In recent years, process-induced mechanical stress has emerged as a useful manufacturing technique that enhances carrier transport and increases drive currents. This improvement in current has helped to compensate the decline of device scaling factors in parameters such as tox, Vth, and Vdd. In this work, we propose stress as a means to achieve optimal power-performance trade-off by combining stress-based,...
Soft errors have emerged as an important reliability challenge for nanoscale VLSI designs. In this paper, we present a fast and efficient soft error rate (SER) computation algorithm for combinational circuits. We first present a novel parametric waveform model based on the Weibull function to represent particle strikes at individual nodes in the circuit. We then describe the construction of the SET...
Reliability failure mechanisms, such as time dependent dielectric breakdown, electromigration, and thermal cycling have become a key concern in processor design. The traditional approach to reliability qualification assumes that the processor operates at maximum performance continuously under worst case voltage and temperature conditions. However, the typical processor spends a very small fraction...
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