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Future 5G wireless systems will deploy massive MIMO systems with large numbers of transmit and receive antennas and novel RF transceiver architectures that admit RF beamforming. Such systems will need to be designed with built-in test and post-manufacture self-tuning capability for yield enhancement and in-field tuning. A key issue is the lack of observability into internal circuit nodes due to the...
Alternative signature based testing of analog/RF circuits and systems has been established over the last two decades. Signature based testing is predicated on signature from device under test (DUT) to statistically predict specifications of an IC. Statistical correlation between specifications and signature are built from a set of initial ICs. Aliasing in signature space will produce aliasing in specification...
High levels of integration in SoCs and SoPs is making pre as well as post-silicon validation of mixed-signal systems increasingly difficult due to: (a) lack of automated pre and postsilicon design checking algorithms and (b) lack of controllability and observability of internal circuit nodes in post-silicon. While digital scan chains provide observability of internal digital circuit states, analog...
Recent studies show that increasing numbers of design bugs are escaping to post-silicon due to the complexity of advanced designs and the lack of adequate verification tools that can validate complex electrical interactions between electrical subsystems on an integrated circuit. In this paper, we present a novel tool for post-silicon validation of mixed-signal/RF circuits through cooperative test...
In the modern mixed-signal SoC design cycle, designers are frequently tasked with detecting and diagnosing behavioral discrepancies between design descriptions given at different levels of hierarchy, e.g. behavioral vs. transistor level descriptions or behavioral/transistor level descriptions vs. fabricated silicon. One problem is detection, to determine if behavioral differences between design descriptions...
Physically Unclonable Function (PUF) circuits are designed to provide part-specific responses that are random across different copies of the circuit by exploiting the unavoidable process variations in nanometer scale fabrication. This property can be used as an important building block in security and cryptographic applications including key generation and challenge-response authentication. A major...
We present a methodology for algorithmic generation of test signals for thedetection and diagnosis of a variety of short and open-circuit defects in analogcircuits. Prior algorithms have focused on test generation for known short oropen defect values. This places the burden of failure coverage on accurateanalysis of observed defects in known failed parts at high cost. In this work, we optimize the...
Technology scaling along with unprecedented levels of device integration has led to increasing numbers of analog/mixed-signal/RF design bugs escaping into silicon. Such bugs are manifested under specific system-on-chip (SoC) operating conditions and their effects are difficult to predict a-priori. This paper describes recent advances in detecting and diagnosing such bugs using "guided" stochastic...
The proliferation of third-party silicon manufacturing has increased the vulnerability of integrated circuits to malicious insertion of hardware for the purpose of leaking secret information or even rendering the circuits useless while deployed in the field. A key goal is to detect the presence of such circuits before they are activated for subversive reasons. One way to achieve this is to detect...
The test generation problem for analog/RF circuits has been largely intractable due to the fact that repetitive circuit simulation for test stimulus optimization is extremely time-consuming. As a consequence, it is difficult, if not impossible, to generate tests for practical mixed-signal/RF circuits that include the effects of tester inaccuracies and measurement noise. To offset this problem and...
Outsourcing of chip manufacturing to untrusted foundries and using third party IPs in design, have opened the possibility of inserting malicious hardware Trojans into the circuit. As excitation of Trojan is extremely rare, it is almost impossible to detect Trojans with functional logic testing. We need to detect Trojans without actually activating it (side channel analysis). Hardware Trojan circuit...
In production testing of analog/RF ICs, application of standard specification-based tests for IC classification is not always an attractive option due to the high costs and test times involved. In this paper, a new test generation algorithm for IC classification is first developed that has the property that the corresponding DUT response signatures for devices from diverse process corners are maximally...
In the recent past, Physically Unclonable Functions (PUFs) have been proposed as a way of implementing security in modern ICs. PUFs are hardware designs that exploit the randomness in silicon manufacturing processes to create IC-specific signatures for silicon authentication. While prior PUF designs have been largely digital, in this work we propose a novel PUF design based on transfer function variability...
Insertion of malicious Trojans into outsourced chip manufacturing generally results in increased capacitances of internal circuit nodes that have been tapped for node controllability and observability by malicious circuitry. Current path delay measurement and side channel Trojan detection techniques are unable to detect Trojans that present low loading to such tapped circuit nodes, especially in the...
As silicon integration complexity increases with 3D stacking and Through-Silicon-Via (TSV), so does the occurrence of memory and IO defects and associated test and validation time. This ultimately leads to an overall cost increase. On a 14nm Intel SOC, a reusable BIST engine called Converged-Pattern-Generator-Checker (CPGC) are architected to detect memory and IO defects, and combined with the software...
As RF design scales to the 28nm technology node and beyond, pre-silicon simulation and verification of complex mixed-signal/RF SoCs is becoming intractable due to the difficulties associated with simulating diverse electrical effects and design bugs. As a consequence, there is increasing pressure to develop comprehensive post-silicon test and debug tools that can be used to identify design bugs and...
To meet the testing requirements of high speed components used in modern communication systems, in an efficient and cost effective manner, it is necessary to develop new device performance measurement techniques that are easily scalable to high frequencies. Traditional up/down conversion based transmitter testing architectures are sensitive to the linearity of the mixers and carrier phase noise in...
With trends in mixed-signal systems-on-chip indicating increasingly extreme scaling of device dimensions and higher levels of integration, the tasks of both design and device validation is becoming increasingly complex. Post-silicon validation of mixed-signaURF systems provides assurances of functionality of complex systems that cannot be asserted by even some of the most advanced simulators. We introduce...
Testing of radio frequency (RF) components such as mixers, amplifiers and voltage controlled oscillators (VCO) traditionally relies on the ability to accurately estimate the device characteristics using down conversion or undersampling based test setups. Efficient and accurate acquisition of the modulating signal either requires a phase locked local oscillator signal or is limited in accuracy. This...
Post-silicon validation of RF/mixed-signal circuits is challenging due to the need to excite all possible operational modes of the DUT in order to establish equivalence between its specified and observed behaviors and to ensure that the DUT does not produce any unexpected behaviors that can lead to system failure. In this research, we first develop a methodology for determining if the DUT contains...
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