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Stringent test-time and yield targets together with increased embedded memory content has resulted in increased power and area of memory self-test and repair logic. It is common for high performance IP cores (CPU/DSP/GPU/etc.) to have embedded BIST datapath (DP) that is shared with functional logic to minimize the IP BIST area overhead and ease IP design-closure. However, different IP cores (from...
The testing of large high-power devices which are destined for 2.5D or 3D applications requires many new techniques and solutions. This paper discusses some of the tradeoffs we looked at when striving to achieve true Known-Good-Devices (KGD) of large thin high-power logic devices. It is expected that the approach explored with this effort will significantly improve the post-assembly 2.5D/3D yield...
To measure a filter's group delay in production is never an easy task and to measure the group delay characteristic in quick and timely manner is difficult to say the least. This paper will discuss a simple method that expands on the author's previous works that will demonstrate how to measure the group delay of a filter and how accurately the technique correlates to measurements of the silicon performance...
Analog/Mixed-Signal test is usually thought of as a quality control step in the manufacture of electronic devices — largely to separate good devices from bad. In this paper, the case is made that analog/mixed-signal semiconductor test technology has been at the forefront of many of today's analog SOC design approaches. This is most likely quite opposite to what most engineers think about test. The...
A practical fault simulation methodology for analog circuits in mixed-signal designs is presented. The methodology leverages the mixed-signal simulation environment of a product and performs mixed-signal fault simulation of embedded analog circuits. A set of open-circuit and short-circuit faults are extracted with guidance from layout parasitics, and automatically injected in to the net list. Fault...
This paper addresses the problem of performing diagnosis using production test results in a test compression environment. For linear response compactors, such as multiple-input shift register (MISRs), diagnosis must be performed from signatures. The key idea in this work is to use symbolic canceling in MISR signatures to extract information from both the MISR signature bits with errors as well as...
Conflict-aware test points, introduced recently, facilitate significant reductions in deterministic test pattern counts. However, dedicated flip-flops driving control points increase test logic area. This paper presents a method to minimize silicon area needed to implement conflict-aware test points by reusing functional flip-flops as drivers of control points. Conflict analysis is applied during...
Today, as LSI devices are increasingly more integrated resulting in larger number of package pins, high speed signal lines are more easily coupled to each other. Additionally, since multisite testing is required to reduce the cost of test, the transmission lines connecting these pins become even more concentrated. To measure these LSI devices, a huge number of high-speed transmission lines are required...
External loopback testing is an industry standard test for serializer-deserializer (SERDES) interfaces, and it is used to test for at-speed defects in the analog transmission (TX) and reception (RX) buffers. The specific test involves sending pseudorandom bit sequence (PRBS) at high speed from the TX side, looping on the load-board and receiving on the RX side where the sequence is checked to calculate...
Diagnosis with a modern day low pin convolution compressor is difficult. Generally, it is done in two steps. In the first step, known as failure mapping, failures are mapped to the scan cells from the faulty responses recorded at compressor outputs on the Automatic Test Equipment (ATE). In the second step, normal scan diagnosis — cone tracing and fault simulation — is used to identify the faulty gate/pin/net...
With the shrinking of technology node, the data retention time of DRAM (DRAM) cells is widespread. Thus, the number of the cells with data retention faults is increased. In this paper, therefore, we propose a built-in self-repair (BISR) scheme for DRAMs using redundancies with physical and logical reconfiguration mechanisms. Spare rows and columns with physical reconfiguration mechanism are used to...
We propose a methodology for dynamically selecting an optimal probe-test flow which reduces test cost without jeopardizing test quality. The granularity of this decision is at the wafer-level and is made before the wafer reaches the probe station, based on an e-test signature which reflects how process variations have affected this particular wafer. The proposed method offers flexibility by optimizing...
Monitoring extrinsic reliability performance in a given technology is often performed in a passive manner. Semiconductor devices (die) are sampled out of production environment, subjected to a series of electrical and mechanical stresses, and finally tested extensively to determine if stressing produced additional fails. This strategy is prone to missing issues which are localized to a lots or wafers...
Defect tolerance can improve system reliability and safety, and IC yield. This paper describes metrics for measuring defect tolerance of a mixed-signal circuit block within an IC. A general metric is defined for defect tolerance at the transistor-level, consistent with ISO 26262, and how it can be measured by an analog defect simulator, for digital and mixed-signal circuits, including those that have...
Much progress has been made in digital microfluidic biochips (DMFB), with a great body of literature addressing low-cost, high-performance, and reliable operation. Despite this progress, security of DMFBs has not been adequately addressed. We present an analysis of a DMFB system prone to malicious modification of routes and propose a DMFB defense based on spatio-temporal randomized checkpoints using...
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