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This work presents the hardware implementation of the RLA (Richardson-Lucy Algorithm) for image restoration task, in which the images are blurred by relative motion between camera and the scene. In this case the RLA was implemented in an FPGA-based platform using the hardware description language VHDL, and assuming the absence of additive noise in the capturing image system. The overall architecture...
An approach is introduced to formally verify the logical correctness of reconfigurable hardware implementations of algebraic operators. Since Hardware Description Languages describe circuits/systems in an imperative style and formalization tools use recursive specification languages, the kernel of our approach is based on a conservative translation from imperative into recursive implementations. The...
This paper introduces a hardware simulation flow that is based on the Xilinx System Generator Tool (XSG), of an architecture for solving dense linear systems, presented as a strongly coupled system, which is in turn based on Gaussian Elimination using an FPGA. A functional verification process is achieved by taking advantage of the XSG, allowing both software and hardware-in-the-loop (HIL) simulations...
Implementation of artificial neural networks in software on general purpose computer platforms are brought to an advanced level both in terms of performance and accuracy. Nonetheless, neural networks are not so easily applied in embedded systems, specially when the fully retraining of the network is required. This paper shows the results of the implementation of artificial neural networks based on...
This work presents an architecture to compute matrix inversions in a hardware reconfigurable FPGA using different floating-point representation precision: single, double and 40-bits. The architectural approach is divided into five principal parts, four modules and one unit, namely Change Row Module, Pivo Module, Matrix Elimination Module, Normalization Module and finally the Gauss-Jordan Control-Circuit...
This paper presents a low cost architecture for the solution of linear equations based on the Gaussian Elimination Method using a reconfigurable system based on FPGA. This architecture can handle single data precision that follows the IEEE 754 floating point standard. The implementation takes advantage of both the internal memory and the DSP blocks (available in the Virtex-5 FPGA). The architectural...
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