The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In recent past, we developed 4×8 and 4×16 processing element (PE) template-based Coarse-Grain Reconfigurable Arrays (CGRAs) and mapped different length and type of Fast Fourier Transform (FFT) algorithms on them. In this paper, we have considered radix-4 and radix-(2, 4) FFT accelerators which were generated from 4 × 8 and 4 × 16 PE CGRA templates respectively. We estimated their power and energy...
One of the major topics that attracts constantly the interest of research community is the acceleration of computationally-intensive applications. Towards this direction, different technologies are competing each other and are all characterized by a common tendency; they evolve continuously towards improving their products so as to serve better their customers and attract new ones. Each company stresses...
Network Congestion can limit the performance of NoC due to increased transmission latency and power consumption. In this paper, to reduce the network congestion, we present an efficient congestion-aware routing method, named Global Load Balancing (GLB). In GLB, packets aggregate and carry congestion information along a path they route. Consequently, this information contains a global view of the path...
The ENOSYS project, funded by the EC, aims to shorten the time-to-market of high-performance SoCs by providing design and tool flows for the design and the implementation of embedded systems by seamless integration of high-level system specifications, software code generation, hardware synthesis, code optimization and design space exploration. The objective here is to automatically generate code,...
We are proposing a system level approach for a fault tolerant heterogeneous multi-processor system-on-chip (HMPSoC) platform that can be customized at design phase according to the requirements and the environmental constraints of the target application. This framework can provide optimal tradeoffs for maximizing the reliability of the system under real-time constraints. The proposed heterogeneous...
3D ICs have emerged as the promising solution for scalability, power consumption and performance demands of next generation Systems-on-Chip (SoC). Along with the advantages, it also imposes lots of challenges in terms of cost efficiency, technological reliability, power, thermal budget and so forth. Networks-on-chip (NoC) is thoroughly investigated in 2D SoC design as scalable interconnects, is also...
We present a framework for the implementation of self-reconfigurable 2D Discrete Cosine Transforms (DCTs). Dynamic Partial Reconfiguration (DPR) and Dynamic Frequency Control lead to a multi-objective optimization scheme that generates Pareto-optimal realizations from the Power-Performance-Accuracy (PPA) space. The PPA space is created by evaluating the 2D DCTs realizations in terms of their power...
With more and more countries opening up sections of unlicensed spectrum for use by TV White Space (TVWS) devices, the prospect of building a device capable of operating in more than one world region is appealing. The difficulty is that the locations of TVWS bands within the radio spectrum are not globally harmonised. With this problem in mind, the purpose of this paper is to present a TVWS transceiver...
Spiking Neural Networks (SNN) consist of fully interconnected computation units (neurons) based on spike processing. This type of networks resembles those found in biological systems studied by neuroscientists. This paper shows a hardware implementation for SNN. First, SNN require the inputs to be spikes, being necessary a conversion system (encoding) from digital values into spikes. For travelling...
This paper studies the implementability of performance efficient multi-lane Polymorphic Register Files (PRFs). Our PRF implementation uses a 2D array of p × q linearly addressable memory banks, with customized addressing functions to avoid address routing circuits. We target one single-view and a set of four non redundant multi-view parallel memory schemes that cover all widely used access patterns...
Encryption and channel coding are both essential steps for reliable, robust and secure operation within wireless networks. Usually, these algorithms are considered independently of each other because of their antagonism, but solutions exist to combine their features into a single simple primitive. This fusion aims to improve the performance and the energy-efficiency of the wireless device while contributing...
In this paper we instigate the design of network interfaces which have knowledge about the transport layer and networking protocols of many-core systems. Workload dynamicity and multitasking are two main features of many-core systems, which are handled by relatively small kernels on each core. In the message-passing paradigm the kernel also acts as the transport layer interface to tasks for exchanging...
Dynamic reconfiguration of hardware resources is increasingly used in applications as a way to increase performances, resources integration or energy efficiency. As this evolution induces a change of the application execution paradigm, various tools have been set up to develop and manage these applications. But most do not allow direct re-use of legacy code, needing adaptation to match the provided...
MARTE has matured into a substantial industrially relevant profile that extends UML expressive power to support the specification and design of embedded systems. When supported by appropriate model transformation and code generation tools, MARTE forms an appropriate starting point for embedded system development. In this paper we propose a simpler yet less powerful subset of MARTE, targeted at multiprocessor...
Current and future computing systems increasingly require that their functionality stays flexible after the system is operational, in order to cope with changing user requirements and improvements in system features, i.e. changing protocols and data-coding standards, evolving demands for support of different user applications, and newly emerging applications in communication, computing and consumer...
Ad-hoc and dynamic adaptation to the requirements of an application enables to increase the energy efficiency of a processor. This method is especially for novel heterogeneous multicore systems of high interest since the various cores can be adapted individually. For this purpose, the current status of the system has to be monitored on the chip. Parameters of interest are the number of communications...
Design space exploration (DSE) of complex embedded systems that combine a number of CPUs, dedicated hardware and software is a tedious task for which a broad range of approaches exists, from the use of high-level models to hardware prototyping. Each of these entails different simulation speed/accuracy tradeoffs, and thereby enables exploring a certain subset of the design space in a given time. Some...
In aerospace application, computational fluid dynamics (CFD) is recognized as a cost effective design tool. UPACS, a package for CFD is convenient for users, which has various solvers to support large scale of complexity. The problem is its computation speed which is hard to be enhanced by using clusters due to its complex memory access patterns. As an economical solution, accelerators using FPGAs...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.