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Encryption and channel coding are both essential steps for reliable, robust and secure operation within wireless networks. Usually, these algorithms are considered independently of each other because of their antagonism, but solutions exist to combine their features into a single simple primitive. This fusion aims to improve the performance and the energy-efficiency of the wireless device while contributing...
Runtime reconfiguration is a promising solution for reducing hardware cost in embedded systems, without compromising on performance. We present a framework that aims to increase the advantages of runtime reconfiguration on reconfigurable processors that support full or partial runtime reconfiguration. The proposed framework incorporates a hierarchical loop partitioning strategy that leverages FPGA-aware...
With the increasing complexity and functionality of Real-Time embedded applications, Multiprocessor System-on-chip “MPSoC” offers the best tradeoffs in computation performances and power consumption. Designing MPSoC projects is time consuming and, often requires several competences and steps, spanning from hardware architecture to mapping application on the platform. This paper presents MPSoCDK, an...
We are proposing a system level approach for a fault tolerant heterogeneous multi-processor system-on-chip (HMPSoC) platform that can be customized at design phase according to the requirements and the environmental constraints of the target application. This framework can provide optimal tradeoffs for maximizing the reliability of the system under real-time constraints. The proposed heterogeneous...
3D ICs have emerged as the promising solution for scalability, power consumption and performance demands of next generation Systems-on-Chip (SoC). Along with the advantages, it also imposes lots of challenges in terms of cost efficiency, technological reliability, power, thermal budget and so forth. Networks-on-chip (NoC) is thoroughly investigated in 2D SoC design as scalable interconnects, is also...
Nowadays, embedded systems become more and more complex: the hardware/software codesign approach is a method to create such systems in a single chip which can be based on reconfigurable technologies such as FPGAs (Field-Programmable Gate Arrays). In such systems, data exchanges are a key point as they convey critical and confidential information and data are transmitted between several hardware modules...
In this paper we instigate the design of network interfaces which have knowledge about the transport layer and networking protocols of many-core systems. Workload dynamicity and multitasking are two main features of many-core systems, which are handled by relatively small kernels on each core. In the message-passing paradigm the kernel also acts as the transport layer interface to tasks for exchanging...
Dynamic reconfiguration of hardware resources is increasingly used in applications as a way to increase performances, resources integration or energy efficiency. As this evolution induces a change of the application execution paradigm, various tools have been set up to develop and manage these applications. But most do not allow direct re-use of legacy code, needing adaptation to match the provided...
This paper presents a tool-supported UML design flow (ENOSYS flow) for designing and implementing embedded systems through the seamless integration of high-level system specification, hardware synthesis, embedded soft VLIW multi-core processors and design space exploration. Using the proposed design flow, investigations into the tradeoffs between various multi-core processor parameters such as the...
The progressive maturity of VLSI manufacturing technology is helping in integrating more and more processing elements and memory units on a single die to form a Multiprocessor System-On-Chip (MPSoC). Network-on-Chip (NoC) is adopted as communication backbone for most of these modern day multiprocessor systems. As complexity of these system scales, there has been a growing concern on the dependability...
We present a framework for the implementation of self-reconfigurable 2D Discrete Cosine Transforms (DCTs). Dynamic Partial Reconfiguration (DPR) and Dynamic Frequency Control lead to a multi-objective optimization scheme that generates Pareto-optimal realizations from the Power-Performance-Accuracy (PPA) space. The PPA space is created by evaluating the 2D DCTs realizations in terms of their power...
In recent past, we developed 4×8 and 4×16 processing element (PE) template-based Coarse-Grain Reconfigurable Arrays (CGRAs) and mapped different length and type of Fast Fourier Transform (FFT) algorithms on them. In this paper, we have considered radix-4 and radix-(2, 4) FFT accelerators which were generated from 4 × 8 and 4 × 16 PE CGRA templates respectively. We estimated their power and energy...
MARTE has matured into a substantial industrially relevant profile that extends UML expressive power to support the specification and design of embedded systems. When supported by appropriate model transformation and code generation tools, MARTE forms an appropriate starting point for embedded system development. In this paper we propose a simpler yet less powerful subset of MARTE, targeted at multiprocessor...
This paper discusses a strategy for translating the Java programming language to a form that is suitable for execution on resource limited embedded systems such as softcore processors in FPGAs, Network-on-Chip nodes and microcontrollers. The translation strategy prioritises the minimisation of runtime memory usage, generated code size, and suitability for a wide range of small architectures over other...
This paper presents the first framework to design and synthesize a formal controller managing dynamic reconfiguration, using a Model Driven Engineering methodology base on an extension of UML/MARTE. The implementation technique highlights the combination of hard configuration constraints using weights (control part) — ensured statically and fulfilled by the managed system at runtime — and soft constraints...
Future advanced embedded computing systems are expected to dynamically adapt applications' behavior and runtime system according to, e.g., usage contexts, operating environments, resources' availability, and battery energy levels. Besides application's functionalities provided by high-level and/or executable binary codes, code for specifying strategies/policies to extend typical functionalities with...
The RIVER architecture is a run-time configurable and programmable fabric for parallel stream processing on FPGAs. RIVER's memory architecture has been designed to support non-trivial data flows efficiently and in real-time. The individual data processing cores are called Dynamic Streaming Engines (DSE). Our cloud computing supported design flow generates hundreds of thousands different DSE cores...
One of the major topics that attracts constantly the interest of research community is the acceleration of computationally-intensive applications. Towards this direction, different technologies are competing each other and are all characterized by a common tendency; they evolve continuously towards improving their products so as to serve better their customers and attract new ones. Each company stresses...
The paper presents the EU funded MADES FP7 project, that aims to develop an effective model driven methodology to evolve current practices for the development of real time embedded systems for avionics and surveillance industries. In MADES, we propose an effective SysML/MARTE language subset and have developed new tools and technologies that support high level design specifications, validation, simulation...
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