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The topology structures of input stage, isolation stage and output stage of power electronic transformer in distribution network were introduced. Using the type of half bridge modular multilevel converter sub module, the dual active bridge and three-phase inverter as the research object, the simulation model of 10kV distribution network power electronic transformer was built based on PSCAD simulation...
In order to avoid the harmonics of traction power supply system delivered to superior power system substation and have a detrimental effect on the quality of public power grid, the scheme, substation equipped with passive filters, processing the problem of harmonics delivered to power system substation was proposed in this paper. Based on the measured data of the system substation, the single-tuned...
This paper describes successful flip-chip package design for 28G-capable SerDes interfaces. Design optimization of the multi-layer 3D vertical BGA area is accomplished using an EM solver to obtain the best possible insertion and return losses given manufacturing capabilities. Several different stripline and microstrip pair-to-pair spacings bearing different amounts of coupling were evaluated in terms...
Digital networking processor power supplies typically have voltage sense points at die level so that the die level voltages are regulated and kept at constant DC levels. In this paper, we studied the load-line effect on the power supplies by simulations and lab measurements. We found that the total dissipated power for digital networking processors can be reduced by the introduction of the load-line...
Two different module referencing schemes, one with split ground planes between transmit/receive (TX/RX), and the other with a common ground plane, are first compared using models generated from 3D full-wave solver, and then the two different module designs are built and tested. The measurements performed and test data on the manufactured modules includes TX output high-low amplitude, eye height, RX...
A well defined power supply tolerance specification is very important for designing processor circuits with sufficient performance margin. We introduce a design flow to derive the voltage tolerance specification by including power noise components due to the significant contributors, namely, voltage drop, voltage gradient, middle frequency chip package resonance noise, high frequency simultaneous...
Bottom Surface Metals (BSM) pin assignment for high frequency signals on a package device is a tedious manual job. Recently, [3] proposed a network flow based method to assign BSM automatically for one layer without routing blockages. In this paper, we extend the work of [3] to do BSM pin assignment on multiple layers with routing blockages. [3] also considers BSM differential pairing constraints,...
For high-speed signaling, differential channels are now commonly used because of the improved noise immunity and receiver sensitivity that can be achieved compared to the single-ended channels that had been widely used in electronic systems until recently. However, single-ended channels have the distinct advantage of only needing one signal trace per signal, which in a well-controlled impedance, low-noise...
In current industry practice, Bottom Surface Metals (BSMs) assignment for high frequency signals on a package device is a tedious manual job. One often needs to change the assignment multiple times in order to produce a routable solution. This paper proposes a network flow based method to assign BSMs automatically. It constructs a network flow graph based on available routing resource, honoring constraints...
In this paper, we present a methodology for minimizing far-end (FE) noise coupling between interconnects in high-speed ceramic modules. The high FE noise coupling between signal interconnects in ceramic modules has been a serious bottleneck for high-performance systems. A methodology employing power/ground mesh planes with minimized orthogonal lines and a via-connected coplanar-type shield (VCS) structure...
Vias in packages and boards, land-grid-array pins, and connector pins introduce significant crosstalk in high-speed differential buses. There are many possible differential signal assignments in those areas that have very different electrical performance. This paper proposes and demonstrates an efficient method to find a large number of possible assignments and assess them to obtain an optimal assignment...
For the first time, compact physical models are derived in this work that enable quick package- and chip-scale calculations of the power supply noise and incorporate the distributed natures of on-chip power/ground grids and package-level power/ground planes. Designers can use these models to perform chip/package co-design for power distribution networks and tradeoff multiple design considerations...
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