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JCT-VC joined by ITU-T VCEG and ISO/IEC MPEG is developing a new video coding standard called HEVC to achieve better coding efficiency for the emerging HD or Ultra HD video content. One of the new coding features in HEVC is increasing intra prediction modes from 9 in H.264/AVC to 35. To reduce the computation time, this paper presents a fast intra mode decision algorithm based on direction energy...
Nowadays, JCT-3V joined by ITU-T VCEG and ISO/IEC MPEG is developing new 3D video coding standard, MVC+D and 3D-AVC, based on H.264/AVC. In addition to color image, depth map is also included to be compressed because of adopting DIBR to generate virtual views. However, the computation complexity of encoder much increases due to additional depth map. This paper presents a new fast intra mode decision...
SOCs designed for embedded systems are now widely used on embedded multimedia devices. Processors in these devices may need capabilities to support some compound computations, and the most important of all is multiply and accumulate (MAC) operation. Thus DSP processors or special ALUs are designed to accelerate these computations. Besides the computation issue, how to improve the reliability, stability...
This paper presents a fast fractional motion estimation (FME) and the associated VLSI architecture for H.264/AVC multiview video coding. The proposed FME automatically turns off the mode P8×8 by exploiting the results of integer motion estimation and similarity between views. In addition, the fraction-pel refinement of integer motion or disparity vector in any partition may be skipped according to...
An adaptive search range algorithm is proposed for multiview motion and disparity estimation. By analyzing the motion and disparity vector distribution in neighboring views and anchor frames respectively, an adequate motion and disparity search range can be chosen. As the search range can be effectively reduced, the saving of computation time of motion and disparity estimation can be up to 73% with...
This demonstration illustrates the fully-hardware-type encoder and decoder that are developed by ITRI (Industrial Technology Research Institute, Taiwan) for 3-D video compression. The encoder and decoder are compliant to ISO/IEC 14496-10 MPEG-4 AVC / ITU-T H.264 standard and they support baseline, main, and high profiles. Both of them also support stereo high profile of the Multiview Video Coding...
In recent years, microcontrollers are largely used in varieties of different systems, especially on small embedded systems, small device controllers, and e-devices. Different from general systems, processors inside these systems may not need very powerful computing capability; however, reliability, robustness, low EMI, and low power are the most important criteria. It is a well-known fact that asynchronous...
We present a fast and low-cost fractional motion estimation (FME) and its corresponding VLSI architecture for H.264/AVC. The proposed direction-based FME algorithm just searches 8 points and employs four hadamard transforms to reduce computation time and hardware cost. Additionally, we propose two mode reduction methods to skip most search modes to further reduce computation complexity. Our FME can...
With the VLSI technology improving rapidly, SoC has been becoming the most important VLSI application. However, clock distribution and low power have already become the two most important issues in SoC design. In addition, it's also a very important issue to integrate IPs that can perform operations correctly with different clocks. Asynchronous circuits may resolve these problems by removing the “clock”...
Motion estimation plays an important role in inter-frame prediction for the video coding standards such as H.264/AVC, MPEG-2, MPEG-4, VC-1, and so on. Its huge computation complexity, however, makes it difficult to achieve real-time coding for the HDTV1080p. In this paper, we propose a dynamic search range algorithm which reduces about 80% of search points in full search algorithm for the H.264/AVC...
We present a high-performance entropy decoding system for H.264/AVC. This system includes a variable length coding (VLC) decoder, a context-based adaptive binary arithmetic coding (CABAC) decoder, and a run-level converter. Each syntax element above slice data is decoded by VLC decoder within a clock cycle. The CABAC decoder decodes the syntax elements at slice data and below through pipeline mechanism...
Nowadays, MPSoCs or multicore processors have been becoming the major trend of system or processor designs. Thus the design of interconnection networks becomes the most important issue of all. However, lots of different problems may arise in the network design and they should be carefully handled. It is widely known that most of these problems can be resolved easily by asynchronous circuits. But because...
We present a high-throughput and low-cost context adaptive binary arithmetic (CABAC) decoder for H.264/AVC. Since the CABAC decoder has strong data dependency while decoding a plurality of bins, we propose a novel pipeline architecture to speed up this operation. Based on different types of syntax elements, two approaches to improve throughput are proposed. In addition, we re-arrange the context models...
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