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This paper reports modeling the parasitic bipolar device in the 40 nm PD SOI NMOS device considering the floating body effect. Using a unique extraction method, the function of the parasitic bipolar device during transient operations could be modeled. During the turn-on transient by imposing a step voltage from 0 V to 2 V at the gate, the case with a slower rise time shows a faster turn-on in the...
In this paper, analysis of the floating-body-effect-related gate tunneling leakage current phenomenon of the 40 nm PD NMOS device using the SPICE bipolar/MOS equivalent circuit approach was reported. From the figure, it was observed that the edge component of the gate-source/gate-drain leakage current (Igs/Igd), which is much smaller than that of the center channel one (Igcs/Igcd), could become negative...
For the first time, an efficient methodology to accurately characterize the gate-bulk leakage current (Igb) and gate capacitance (Cgg) of PD SOI floating body (FB) devices was proposed and demonstrated in 40-nm PD SOI devices with ultra-thin oxide EOT 12 A. By applying the RF testing skill for the proposed SOI test patterns, we can eliminate properly the parasitic elements due to the co-existence...
This paper reports an analysis of the STI-induced mechanical stress-related breakdown characteristics of the 40 nm PD SOI NMOS device with a closed-form formula. As verified by the experimentally measured data, the 2D simulation results and the closed-form formula, the breakdown voltage becomes higher for the device with a smaller S/D length of 0.17 ??m due to the weaker function of the parasitic...
This letter reports the shallow-trench-isolation (STI)-induced mechanical-stress-related breakdown behavior of the 40-nm PD-SOI NMOS device. As verified by the experimentally measured data and the 2D simulation results, breakdown occurs at a higher drain voltage for the device with a smaller S/D length of 0.17 mum due to the weaker function of the parasitic bipolar device, which is offset by the stronger...
For nanometer-regime PD SOI CMOS devices, the S/D region may be very small-the influence of the STI-induced mechanical stress cannot be neglected. In this paper, the influence of STI-induced mechanical stress in the subthrehsold kink behavior of a 40nm PD SOI NMOS device is reported.
The mechanical stress induced by shallow trench isolation (STI) may affect the performance of CMOS devices. Mechanical stress may change workfunction, effective mass, carrrier mobility, and junction leakage. This paper reports the influence of STI-induced mechanical stress in the kink effect of a 65 nm PD SOI NMOS device.
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