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The dependence with the measurement frequency observed in the Capacitance-Voltage characteristics of Metal-Insulator-Semiconductor structures using an amorphous oxide semiconductor material is presented and analyzed. It is demonstrated by simulation that the effect is due to the Distribution of States (DOS) present in the energy gap of the semiconductor material and strongly depends on the capture...
The microelectronics industry has progressed astonishingly along several decades, thanks to the MOS transistor shrinkage. However, the parasitic gate capacitance becomes an important concern for device behavior optimization in the nanometric range. The fringing parasitic gate capacitance exhibits weaker channel length dependence than the intrinsic counterpart. For this reason, the relative weight...
These last years, the triple‐gate fin field‐effect transistor (FinFET) has appeared as attractive candidate to pursue the complementary metal‐oxide semiconductor technology roadmap for digital and analog applications. However, the development of analog applications requires models that properly describe the static and RF behaviors as well as the extrinsic parameters related to the three‐dimensional...
In this paper, a semi-analytical extrinsic gate capacitance model for Triple Gate FinFET, based on three-dimensional numerical simulations, is presented. The model takes into account the source/drain electrode and contact areas. It includes 5 capacitance components that describe the different fringing electrical couplings that exist inside the FinFET structure. The semi-analytical model accurately...
In this paper, we develop an analytical model to simulate strained silicon NMOSFETs, which allows to describe the drain current. Numerical simulations were performed in order to validate the model, where different technological parameters were considered (e.g. impurity concentrations in Si1−yGey and strained-silicon films). A good agreement with numerical simulations has been obtained.
Modeling of the small-signal equivalent circuit of SOI FinFETs through SPICE simulations is presented. A compact model implemented in Verilog-A predicts well the DC characteristics of RF SOI FinFETs and allows the extraction of the intrinsic conductance, transconductance and capacitances at any selected operating point. The intrinsic small-signal equivalent circuit composed of those extracted lumped...
Triple-Gate FinFETs have been demonstrated to be promising to push further the down scaling of the CMOS technology, thanks to their high immunity against the so-called short channel effects. However, due to their three-dimensional (3-D) architecture, strong degradation of their analog characteristics has been reported, basically due to large extrinsic resistances and capacitances. In this paper, based...
In the last years the MOS transistor technology has reach very high cut-off frequencies (near to 500 GHz), thanks to the continuous reduction of the channel length, but the short-channel-effects (SCE) strongly affects the MOSFET behavior below 60 nm. For such technology nodes the Multiple-Gate transistor (MuGFET) appears as a promising alternative to continue with the International Technology Roadmap...
In the last few years, many efforts have been made looking for the improvement of the DC and RF performance of MOS transistors. In this scope, Schottky-Barrier transistors appear as very interesting alternative to conventional devices. In this paper we present the non-linear behavior of dopant segregated n-type SB-MOSFETs with 180 nm channel length.
A compact model for small-signal equivalent circuit of DG-MOSFETs is presented. The intrinsic parameters are obtained from DC analytic compact model. This DC model allows determining the mobile charge inside the transistor channel, from which the intrinsic parameters are derived. Additionally, the extrinsic capacitances are calculated and included into the model. This compact small-signal model allows...
A new extraction method of the intrinsic parameters of the small-signal equivalent circuit model of SOI MOS transistors (MOSFET) is presented. This new method does not need the previous knowledge of the extrinsic series resistances, moreover, it is possible to directly determine the intrinsic parameters at the bias point of interest. Floating-Body SOI MOSFETs are analyzed using this method.
The modeling of MOS transistors used for RF applications needs the definition of a lumped equivalent circuit where the intrinsic device and series extrinsic resistances are properly evaluated. The model accuracy depends on the extraction precision of each intrinsic lumped element. In order to determine the intrinsic device behavior, it is necessary to first remove the series extrinsic resistances...
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