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Fault-free function and defect tolerance are key requirements for modern embedded systems. To meet time-to-market constraints, complex IP-components are used to assemble even more complex semiconductor products. Often, trust is required since these IPs are developed, verified and tested by external third-party IP-providers. In this work, we focus specifically on processor-IPs. A method for run-time...
The recent advances with respect to the costs, size, and power consumption of electronic components paved the way for System of Systems (SoS), Cyber-Physical Systems (CPS), or the Internet of Things (IoT). As a next stage, these developments currently motivate the consideration of Complex Swarm Systems (CSS), i.e., continuously running systems that will dynamically change after deployment and are...
Verification and validation of UML/OCL models is a crucial task in the design of complex software/hardware systems. The behavior in those models is expressed in terms of operations with pre- and postconditions. These, however, are often not precise enough to describe what may or may not be modified in a transition between two system states. This frame problem is commonly addressed by providing additional...
In the last years, partial reconfigurable systems (PRSs) have included Networks-on-Chip (NoCs) as their communication structure. The problem of mapping and positioning in NoCs have been extended to PSRs. Mapping of cores in NoCs aims to find the best topological location onto the NoC, such that the metrics of interest can be greatly optimized. The placement problem deals with the allocation of those...
In the last years, Field programmable gate-arrays (FPGAs) with partial reconfiguration capabilities have raised interest in the implementation of dynamically reconfigurable systems (DSRs). For dealing with the issue of communication between reconfigurable and fixed partitions, Networks-on-Chip (NoCs) have gained importance in DSR architectures. The mapping of cores in NoCs aims to find the best topological...
In the last years, Field programmable gate-arrays (FPGAs) with partial reconfiguration capabilities have raised interest in the implementation of dynamically reconfigurable systems. It has not become a mainstream activity though, due to the lack of solid design methodologies and associated tools. One of the approaches aimed to free the designer of lower level implementation details is to use structured...
This paper presents an hardware implementation of the Sequential Minimal Optimization (SMO) for the Support Vector Machine (SVM) training phase. A general-purpose reconfigurable architecture, aimed to partial reconfiguration FPGAs, is developed, i.e., it supports different sizes of training sets, with wide-range number of samples and elements. The effects of fixed-point implementation are analyzed...
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